08d61139be
Support add and delete operations on flow director filter. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
605 lines
18 KiB
C
605 lines
18 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2020
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*/
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#ifndef _TXGBE_ETHDEV_H_
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#define _TXGBE_ETHDEV_H_
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#include <stdint.h>
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#include "base/txgbe.h"
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#include "txgbe_ptypes.h"
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#include <rte_flow.h>
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#include <rte_flow_driver.h>
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#include <rte_time.h>
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#include <rte_ethdev.h>
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#include <rte_ethdev_core.h>
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#include <rte_hash.h>
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#include <rte_hash_crc.h>
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/* need update link, bit flag */
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#define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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#define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
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#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
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#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
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#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
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/*
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* Defines that were not part of txgbe_type.h as they are not used by the
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* FreeBSD driver.
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*/
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#define TXGBE_VFTA_SIZE 128
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#define TXGBE_VLAN_TAG_SIZE 4
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#define TXGBE_HKEY_MAX_INDEX 10
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/*Default value of Max Rx Queue*/
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#define TXGBE_MAX_RX_QUEUE_NUM 128
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#define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
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#ifndef NBBY
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#define NBBY 8 /* number of bits in a byte */
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#endif
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#define TXGBE_HWSTRIP_BITMAP_SIZE \
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(TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
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#define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
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#define TXGBE_MAX_QUEUE_NUM_PER_VF 8
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#define TXGBE_5TUPLE_MAX_PRI 7
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#define TXGBE_5TUPLE_MIN_PRI 1
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#define TXGBE_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_IPV6_EX | \
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ETH_RSS_IPV6_TCP_EX | \
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ETH_RSS_IPV6_UDP_EX)
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#define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
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#define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
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#define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
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#define TXGBE_MAX_L2_TN_FILTER_NUM 128
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/*
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* Information about the fdir mode.
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*/
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struct txgbe_hw_fdir_mask {
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uint16_t vlan_tci_mask;
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uint32_t src_ipv4_mask;
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uint32_t dst_ipv4_mask;
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uint16_t src_ipv6_mask;
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uint16_t dst_ipv6_mask;
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uint16_t src_port_mask;
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uint16_t dst_port_mask;
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uint16_t flex_bytes_mask;
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uint8_t mac_addr_byte_mask;
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uint32_t tunnel_id_mask;
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uint8_t tunnel_type_mask;
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};
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struct txgbe_fdir_filter {
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TAILQ_ENTRY(txgbe_fdir_filter) entries;
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struct txgbe_atr_input input; /* key of fdir filter*/
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uint32_t fdirflags; /* drop or forward */
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uint32_t fdirhash; /* hash value for fdir */
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uint8_t queue; /* assigned rx queue */
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};
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/* list of fdir filters */
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TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
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struct txgbe_fdir_rule {
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struct txgbe_hw_fdir_mask mask;
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struct txgbe_atr_input input; /* key of fdir filter */
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bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
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bool b_mask; /* If TRUE, mask has meaning. */
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enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
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uint32_t fdirflags; /* drop or forward */
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uint32_t soft_id; /* an unique value for this rule */
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uint8_t queue; /* assigned rx queue */
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uint8_t flex_bytes_offset;
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};
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struct txgbe_hw_fdir_info {
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struct txgbe_hw_fdir_mask mask;
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uint8_t flex_bytes_offset;
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uint16_t collision;
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uint16_t free;
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uint16_t maxhash;
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uint8_t maxlen;
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uint64_t add;
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uint64_t remove;
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uint64_t f_add;
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uint64_t f_remove;
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struct txgbe_fdir_filter_list fdir_list; /* filter list*/
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/* store the pointers of the filters, index is the hash value. */
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struct txgbe_fdir_filter **hash_map;
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struct rte_hash *hash_handle; /* cuckoo hash handler */
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bool mask_added; /* If already got mask from consistent filter */
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};
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/* structure for interrupt relative data */
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struct txgbe_interrupt {
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uint32_t flags;
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uint32_t mask_misc;
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/* to save original mask during delayed handler */
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uint32_t mask_misc_orig;
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uint32_t mask[2];
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};
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#define TXGBE_NB_STAT_MAPPING 32
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#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
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#define NB_QMAP_FIELDS_PER_QSM_REG 4
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#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
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struct txgbe_stat_mappings {
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uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
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uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
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};
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struct txgbe_vfta {
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uint32_t vfta[TXGBE_VFTA_SIZE];
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};
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struct txgbe_hwstrip {
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uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
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};
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/*
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* VF data which used by PF host only
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*/
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#define TXGBE_MAX_VF_MC_ENTRIES 30
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struct txgbe_uta_info {
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uint8_t uc_filter_type;
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uint16_t uta_in_use;
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uint32_t uta_shadow[TXGBE_MAX_UTA];
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};
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#define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
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struct txgbe_mirror_info {
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struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
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/* store PF mirror rules configuration */
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};
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struct txgbe_vf_info {
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uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
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uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
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uint16_t num_vf_mc_hashes;
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bool clear_to_send;
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uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
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uint16_t vlan_count;
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uint8_t api_version;
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uint16_t switch_domain_id;
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uint16_t xcast_mode;
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uint16_t mac_count;
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};
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TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
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struct txgbe_5tuple_filter_info {
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uint32_t dst_ip;
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uint32_t src_ip;
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uint16_t dst_port;
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uint16_t src_port;
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enum txgbe_5tuple_protocol proto; /* l4 protocol. */
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uint8_t priority; /* seven levels (001b-111b), 111b is highest,
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* used when more than one filter matches.
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*/
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uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
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src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
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dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
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src_port_mask:1, /* if mask is 1b, do not compare src port. */
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proto_mask:1; /* if mask is 1b, do not compare protocol. */
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};
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/* 5tuple filter structure */
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struct txgbe_5tuple_filter {
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TAILQ_ENTRY(txgbe_5tuple_filter) entries;
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uint16_t index; /* the index of 5tuple filter */
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struct txgbe_5tuple_filter_info filter_info;
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uint16_t queue; /* rx queue assigned to */
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};
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#define TXGBE_5TUPLE_ARRAY_SIZE \
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(RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
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(sizeof(uint32_t) * NBBY))
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struct txgbe_ethertype_filter {
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uint16_t ethertype;
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uint32_t etqf;
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uint32_t etqs;
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/**
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* If this filter is added by configuration,
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* it should not be removed.
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*/
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bool conf;
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};
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/*
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* Structure to store filters' info.
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*/
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struct txgbe_filter_info {
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uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
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/* store used ethertype filters*/
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struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
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/* Bit mask for every used 5tuple filter */
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uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
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struct txgbe_5tuple_filter_list fivetuple_list;
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/* store the SYN filter info */
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uint32_t syn_info;
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};
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struct txgbe_l2_tn_key {
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enum rte_eth_tunnel_type l2_tn_type;
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uint32_t tn_id;
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};
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struct txgbe_l2_tn_filter {
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TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
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struct txgbe_l2_tn_key key;
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uint32_t pool;
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};
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TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
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struct txgbe_l2_tn_info {
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struct txgbe_l2_tn_filter_list l2_tn_list;
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struct txgbe_l2_tn_filter **hash_map;
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struct rte_hash *hash_handle;
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bool e_tag_en; /* e-tag enabled */
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bool e_tag_fwd_en; /* e-tag based forwarding enabled */
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uint16_t e_tag_ether_type; /* ether type for e-tag */
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};
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/* The configuration of bandwidth */
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struct txgbe_bw_conf {
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uint8_t tc_num; /* Number of TCs. */
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};
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/*
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* Structure to store private data for each driver instance (for each port).
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*/
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struct txgbe_adapter {
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struct txgbe_hw hw;
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struct txgbe_hw_stats stats;
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struct txgbe_hw_fdir_info fdir;
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struct txgbe_interrupt intr;
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struct txgbe_stat_mappings stat_mappings;
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struct txgbe_vfta shadow_vfta;
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struct txgbe_hwstrip hwstrip;
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struct txgbe_dcb_config dcb_config;
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struct txgbe_mirror_info mr_data;
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struct txgbe_vf_info *vfdata;
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struct txgbe_uta_info uta_info;
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struct txgbe_filter_info filter;
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struct txgbe_l2_tn_info l2_tn;
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struct txgbe_bw_conf bw_conf;
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bool rx_bulk_alloc_allowed;
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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/* For RSS reta table update */
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uint8_t rss_reta_updated;
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};
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#define TXGBE_DEV_ADAPTER(dev) \
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((struct txgbe_adapter *)(dev)->data->dev_private)
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#define TXGBE_DEV_HW(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
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#define TXGBE_DEV_STATS(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
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#define TXGBE_DEV_INTR(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
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#define TXGBE_DEV_FDIR(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
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#define TXGBE_DEV_STAT_MAPPINGS(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
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#define TXGBE_DEV_VFTA(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
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#define TXGBE_DEV_HWSTRIP(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
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#define TXGBE_DEV_DCB_CONFIG(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
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#define TXGBE_DEV_VFDATA(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
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#define TXGBE_DEV_MR_INFO(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
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#define TXGBE_DEV_UTA_INFO(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
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#define TXGBE_DEV_FILTER(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
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#define TXGBE_DEV_L2_TN(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
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#define TXGBE_DEV_BW_CONF(dev) \
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(&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
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/*
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* RX/TX function prototypes
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*/
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void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
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void txgbe_dev_free_queues(struct rte_eth_dev *dev);
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void txgbe_dev_rx_queue_release(void *rxq);
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void txgbe_dev_tx_queue_release(void *txq);
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int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
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int txgbe_dev_rx_init(struct rte_eth_dev *dev);
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void txgbe_dev_tx_init(struct rte_eth_dev *dev);
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int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
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void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
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void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
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void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
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void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
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int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_rxq_info *qinfo);
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void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_txq_info *qinfo);
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uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
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int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
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struct rte_eth_ntuple_filter *filter,
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bool add);
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int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
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struct rte_eth_ethertype_filter *filter,
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bool add);
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int txgbe_syn_filter_set(struct rte_eth_dev *dev,
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struct rte_eth_syn_filter *filter,
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bool add);
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/**
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* l2 tunnel configuration.
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*/
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struct txgbe_l2_tunnel_conf {
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enum rte_eth_tunnel_type l2_tunnel_type;
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uint16_t ether_type; /* ether type in l2 header */
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uint32_t tunnel_id; /* port tag id for e-tag */
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uint16_t vf_id; /* VF id for tag insertion */
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uint32_t pool; /* destination pool for tag based forwarding */
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|
};
|
|
|
|
int
|
|
txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
|
|
struct txgbe_l2_tunnel_conf *l2_tunnel,
|
|
bool restore);
|
|
int
|
|
txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
|
|
struct txgbe_l2_tunnel_conf *l2_tunnel);
|
|
void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
|
|
uint8_t queue, uint8_t msix_vector);
|
|
|
|
/*
|
|
* Flow director function prototypes
|
|
*/
|
|
int txgbe_fdir_configure(struct rte_eth_dev *dev);
|
|
int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
|
|
int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
|
|
uint16_t offset);
|
|
int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
|
|
struct txgbe_fdir_rule *rule,
|
|
bool del, bool update);
|
|
|
|
void txgbe_configure_pb(struct rte_eth_dev *dev);
|
|
void txgbe_configure_port(struct rte_eth_dev *dev);
|
|
void txgbe_configure_dcb(struct rte_eth_dev *dev);
|
|
|
|
int
|
|
txgbe_dev_link_update_share(struct rte_eth_dev *dev,
|
|
int wait_to_complete);
|
|
int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
|
|
|
|
void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
|
|
|
|
void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
|
|
|
|
int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
|
|
|
|
uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
|
|
|
|
void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
|
|
|
|
extern const struct rte_flow_ops txgbe_flow_ops;
|
|
|
|
int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
|
|
uint16_t tx_rate, uint64_t q_msk);
|
|
int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
|
|
uint16_t tx_rate);
|
|
static inline int
|
|
txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
|
|
uint16_t ethertype)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
|
|
if (filter_info->ethertype_filters[i].ethertype == ethertype &&
|
|
(filter_info->ethertype_mask & (1 << i)))
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static inline int
|
|
txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
|
|
struct txgbe_ethertype_filter *ethertype_filter)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
|
|
if (filter_info->ethertype_mask & (1 << i))
|
|
continue;
|
|
|
|
filter_info->ethertype_mask |= 1 << i;
|
|
filter_info->ethertype_filters[i].ethertype =
|
|
ethertype_filter->ethertype;
|
|
filter_info->ethertype_filters[i].etqf =
|
|
ethertype_filter->etqf;
|
|
filter_info->ethertype_filters[i].etqs =
|
|
ethertype_filter->etqs;
|
|
filter_info->ethertype_filters[i].conf =
|
|
ethertype_filter->conf;
|
|
break;
|
|
}
|
|
return (i < TXGBE_ETF_ID_MAX ? i : -1);
|
|
}
|
|
|
|
static inline int
|
|
txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
|
|
uint8_t idx)
|
|
{
|
|
if (idx >= TXGBE_ETF_ID_MAX)
|
|
return -1;
|
|
filter_info->ethertype_mask &= ~(1 << idx);
|
|
filter_info->ethertype_filters[idx].ethertype = 0;
|
|
filter_info->ethertype_filters[idx].etqf = 0;
|
|
filter_info->ethertype_filters[idx].etqs = 0;
|
|
filter_info->ethertype_filters[idx].etqs = FALSE;
|
|
return idx;
|
|
}
|
|
|
|
/* High threshold controlling when to start sending XOFF frames. */
|
|
#define TXGBE_FC_XOFF_HITH 128 /*KB*/
|
|
/* Low threshold controlling when to start sending XON frames. */
|
|
#define TXGBE_FC_XON_LOTH 64 /*KB*/
|
|
|
|
/* Timer value included in XOFF frames. */
|
|
#define TXGBE_FC_PAUSE_TIME 0x680
|
|
|
|
#define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
|
|
#define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
|
|
#define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
|
|
|
|
/*
|
|
* Default values for RX/TX configuration
|
|
*/
|
|
#define TXGBE_DEFAULT_RX_FREE_THRESH 32
|
|
#define TXGBE_DEFAULT_RX_PTHRESH 8
|
|
#define TXGBE_DEFAULT_RX_HTHRESH 8
|
|
#define TXGBE_DEFAULT_RX_WTHRESH 0
|
|
|
|
#define TXGBE_DEFAULT_TX_FREE_THRESH 32
|
|
#define TXGBE_DEFAULT_TX_PTHRESH 32
|
|
#define TXGBE_DEFAULT_TX_HTHRESH 0
|
|
#define TXGBE_DEFAULT_TX_WTHRESH 0
|
|
|
|
/* Additional timesync values. */
|
|
#define NSEC_PER_SEC 1000000000L
|
|
#define TXGBE_INCVAL_10GB 0xCCCCCC
|
|
#define TXGBE_INCVAL_1GB 0x800000
|
|
#define TXGBE_INCVAL_100 0xA00000
|
|
#define TXGBE_INCVAL_10 0xC7F380
|
|
#define TXGBE_INCVAL_FPGA 0x800000
|
|
#define TXGBE_INCVAL_SHIFT_10GB 20
|
|
#define TXGBE_INCVAL_SHIFT_1GB 18
|
|
#define TXGBE_INCVAL_SHIFT_100 15
|
|
#define TXGBE_INCVAL_SHIFT_10 12
|
|
#define TXGBE_INCVAL_SHIFT_FPGA 17
|
|
|
|
#define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
|
|
|
|
/* store statistics names and its offset in stats structure */
|
|
struct rte_txgbe_xstats_name_off {
|
|
char name[RTE_ETH_XSTATS_NAME_SIZE];
|
|
unsigned int offset;
|
|
};
|
|
|
|
const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
|
int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
|
|
struct rte_ether_addr *mc_addr_set,
|
|
uint32_t nb_mc_addr);
|
|
int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
uint16_t reta_size);
|
|
int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
uint16_t reta_size);
|
|
void txgbe_dev_setup_link_alarm_handler(void *param);
|
|
void txgbe_read_stats_registers(struct txgbe_hw *hw,
|
|
struct txgbe_hw_stats *hw_stats);
|
|
|
|
void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
|
|
void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
|
|
void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
|
|
void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
|
|
uint16_t queue, bool on);
|
|
void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
|
|
int mask);
|
|
|
|
#endif /* _TXGBE_ETHDEV_H_ */
|