9481b0902e
The driver must send its version information to the firmware, so the firmware knows the driver is up. Otherwise, it will cause unexpected OS package downloading when multiple driver instances running on the same device. Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
204 lines
7.5 KiB
C
204 lines
7.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2019
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*/
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#ifndef _ICE_COMMON_H_
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#define _ICE_COMMON_H_
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#include "ice_type.h"
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#include "ice_flex_pipe.h"
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#include "ice_switch.h"
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#include "ice_fdir.h"
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enum ice_fw_modes {
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ICE_FW_MODE_NORMAL,
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ICE_FW_MODE_DBG,
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ICE_FW_MODE_REC,
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ICE_FW_MODE_DBG_REC
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};
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enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
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void
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ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len);
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enum ice_status ice_init_hw(struct ice_hw *hw);
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void ice_deinit_hw(struct ice_hw *hw);
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enum ice_status ice_check_reset(struct ice_hw *hw);
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enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
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enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
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void ice_shutdown_all_ctrlq(struct ice_hw *hw);
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enum ice_status
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ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_rq_event_info *e, u16 *pending);
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enum ice_status
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ice_get_link_status(struct ice_port_info *pi, bool *link_up);
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enum ice_status
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ice_update_link_info(struct ice_port_info *pi);
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enum ice_status
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ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
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enum ice_aq_res_access_type access, u32 timeout);
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void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
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enum ice_status
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ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
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enum ice_status
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ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
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enum ice_status
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ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
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struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
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enum ice_adminq_opc opc, struct ice_sq_cd *cd);
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enum ice_status ice_init_nvm(struct ice_hw *hw);
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enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
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enum ice_status
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ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
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enum ice_status
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ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_aq_desc *desc, void *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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void ice_clear_pxe_mode(struct ice_hw *hw);
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enum ice_status ice_get_caps(struct ice_hw *hw);
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/* Define a macro that will align a pointer to point to the next memory address
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* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
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* example, given the variable pointer = 0x1006, then after the following call:
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*
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* pointer = ICE_ALIGN(pointer, 4)
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*
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* ... the value of pointer would equal 0x1008, since 0x1008 is the next
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* address after 0x1006 which is divisible by 4.
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*/
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#define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
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enum ice_status
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ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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u32 rxq_index);
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#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
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enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
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enum ice_status
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ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
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enum ice_status
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ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
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struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
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u32 tx_cmpltnq_index);
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enum ice_status
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ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
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enum ice_status
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ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
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struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
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u32 tx_drbell_q_index);
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#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
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enum ice_status
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ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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u16 lut_size);
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enum ice_status
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ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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u16 lut_size);
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enum ice_status
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ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
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struct ice_aqc_get_set_rss_keys *keys);
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enum ice_status
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ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
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struct ice_aqc_get_set_rss_keys *keys);
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enum ice_status
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ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
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struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
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struct ice_sq_cd *cd);
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bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
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enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
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void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
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extern const struct ice_ctx_ele ice_tlan_ctx_info[];
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enum ice_status
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ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
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enum ice_status
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ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
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void *buf, u16 buf_size, struct ice_sq_cd *cd);
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enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
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struct ice_aqc_get_phy_caps_data *caps,
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struct ice_sq_cd *cd);
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void
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ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
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u16 link_speeds_bitmap);
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enum ice_status
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ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
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struct ice_sq_cd *cd);
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enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
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enum ice_status
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ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
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struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
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enum ice_status
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ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
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bool ena_auto_link_update);
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void
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ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
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void
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ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
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struct ice_aqc_set_phy_cfg_data *cfg);
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enum ice_status
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ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
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struct ice_link_status *link, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
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enum ice_status
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ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
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u16 *q_handle, u16 *q_ids, u32 *q_teids,
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enum ice_disq_rst_src rst_src, u16 vmvf_num,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
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u16 *max_lanqs);
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enum ice_status
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ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
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u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
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void ice_replay_post(struct ice_hw *hw);
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void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
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void ice_sched_replay_agg(struct ice_hw *hw);
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enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);
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enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
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enum ice_status
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ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
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enum ice_rl_type rl_type, u8 bw_alloc);
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enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
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void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
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void
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ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
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bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat);
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void
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ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
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u64 *prev_stat, u64 *cur_stat);
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enum ice_status
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ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
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struct ice_aqc_get_elem *buf);
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bool ice_is_fw_in_rec_mode(struct ice_hw *hw);
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#endif /* _ICE_COMMON_H_ */
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