9c4491cf5c
Adding feature file and guide for OCTEON TX crypto PMD Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
128 lines
3.6 KiB
ReStructuredText
128 lines
3.6 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2018 Cavium, Inc
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Cavium OCTEON TX Crypto Poll Mode Driver
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========================================
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The OCTEON TX crypto poll mode driver provides support for offloading
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cryptographic operations to cryptographic accelerator units on
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**OCTEON TX** :sup:`®` family of processors (CN8XXX). The OCTEON TX crypto
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poll mode driver enqueues the crypto request to this accelerator and dequeues
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the response once the operation is completed.
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Supported Algorithms
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--------------------
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Cipher Algorithms
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~~~~~~~~~~~~~~~~~
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* ``RTE_CRYPTO_CIPHER_NULL``
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* ``RTE_CRYPTO_CIPHER_3DES_CBC``
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* ``RTE_CRYPTO_CIPHER_3DES_ECB``
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* ``RTE_CRYPTO_CIPHER_AES_CBC``
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* ``RTE_CRYPTO_CIPHER_AES_CTR``
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* ``RTE_CRYPTO_CIPHER_AES_XTS``
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* ``RTE_CRYPTO_CIPHER_DES_CBC``
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* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
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* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
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* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
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Hash Algorithms
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~~~~~~~~~~~~~~~
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* ``RTE_CRYPTO_AUTH_NULL``
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* ``RTE_CRYPTO_AUTH_AES_GMAC``
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* ``RTE_CRYPTO_AUTH_KASUMI_F9``
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* ``RTE_CRYPTO_AUTH_MD5``
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* ``RTE_CRYPTO_AUTH_MD5_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA1``
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* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA224``
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* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA256``
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* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA384``
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* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA512``
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* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
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* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
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* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
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AEAD Algorithms
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~~~~~~~~~~~~~~~
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* ``RTE_CRYPTO_AEAD_AES_GCM``
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Compilation
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-----------
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The **OCTEON TX** :sup:`®` board must be running the linux kernel based on
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sdk-6.2.0 patch 3. In this, the OCTEON TX crypto PF driver is already built in.
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For compiling the OCTEON TX crypto poll mode driver, please check if the
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CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in
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config/common_base file.
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* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y``
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The following are the steps to compile the OCTEON TX crypto poll mode driver:
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.. code-block:: console
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cd <dpdk directory>
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make config T=arm64-thunderx-linuxapp-gcc
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make
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The example applications can be compiled using the following:
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.. code-block:: console
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cd <dpdk directory>
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export RTE_SDK=$PWD
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export RTE_TARGET=build
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cd examples/<application>
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make
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Execution
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---------
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The number of crypto VFs to be enabled can be controlled by setting sysfs entry,
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`sriov_numvfs`, for the corresponding PF driver.
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.. code-block:: console
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echo <num_vfs> > /sys/bus/pci/devices/<dev_bus_id>/sriov_numvfs
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The device bus ID, `dev_bus_id`, to be used in the above step can be found out
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by using dpdk-devbind.py script. The OCTEON TX crypto PF device need to be
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identified and the corresponding device number can be used to tune various PF
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properties.
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Once the required VFs are enabled, dpdk-devbind.py script can be used to
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identify the VFs. To be accessible from DPDK, VFs need to be bound to vfio-pci
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driver:
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.. code-block:: console
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cd <dpdk directory>
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./usertools/dpdk-devbind.py -u <vf device no>
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./usertools/dpdk-devbind.py -b vfio-pci <vf device no>
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Appropriate huge page need to be setup in order to run the DPDK example
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applications.
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.. code-block:: console
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echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
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mkdir /mnt/huge
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mount -t hugetlbfs nodev /mnt/huge
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Example applications can now be executed with crypto operations offloaded to
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OCTEON TX crypto PMD.
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.. code-block:: console
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./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
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"(1,0,0),(0,0,0)" -f ep1.cfg
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