34a90f8665
Modify pipe level functions to allow different subports of the same port to have different configuration in terms of number of pipes, pipe queue sizes, etc. Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com> Signed-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>
38 lines
624 B
Plaintext
38 lines
624 B
Plaintext
DPDK_2.0 {
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global:
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rte_approx;
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rte_red_config_init;
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rte_red_log2_1_minus_Wq;
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rte_red_pow2_frac_inv;
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rte_red_rand_seed;
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rte_red_rand_val;
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rte_red_rt_data_init;
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rte_sched_pipe_config;
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rte_sched_port_config;
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rte_sched_port_dequeue;
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rte_sched_port_enqueue;
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rte_sched_port_free;
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rte_sched_port_get_memory_footprint;
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rte_sched_queue_read_stats;
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rte_sched_subport_config;
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rte_sched_subport_read_stats;
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local: *;
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};
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DPDK_2.1 {
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global:
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rte_sched_port_pkt_write;
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rte_sched_port_pkt_read_tree_path;
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rte_sched_port_pkt_read_color;
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} DPDK_2.0;
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EXPERIMENTAL {
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global:
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rte_sched_subport_pipe_profile_add;
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};
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