7e2c3e17fe
This patch adds the implementation of the 128-bit atomic compare exchange API on aarch64. Using 64-bit 'ldxp/stxp' instructions can perform this operation. Moreover, on the LSE atomic extension accelerated platforms, it is implemented by 'casp' instructions for better performance. Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, this patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable the 'cas' version on older version compilers. For octeontx2, we make sure that the lse (and other) extensions are enabled even if the compiler does not know of the octeontx2 target cpu. Since direct x0 register used in the code and cas_op_name() and rte_atomic128_cmp_exchange() is inline function, based on parent function load, it may corrupt x0 register aka break aarch64 ABI. Define CAS operations as rte_noinline functions to avoid an ABI break [1]. 1: https://git.dpdk.org/dpdk/commit/?id=5b40ec6b9662 Suggested-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Phil Yang <phil.yang@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Tested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Reviewed-by: David Marchand <david.marchand@redhat.com>
13 lines
282 B
Plaintext
13 lines
282 B
Plaintext
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2018 Marvell International Ltd
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#
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#include "defconfig_arm64-armv8a-linux-gcc"
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CONFIG_RTE_MACHINE="thunderx2"
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CONFIG_RTE_CACHE_LINE_SIZE=64
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CONFIG_RTE_MAX_NUMA_NODES=2
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CONFIG_RTE_MAX_LCORE=256
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CONFIG_RTE_ARM_FEATURE_ATOMICS=y
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