f9aaa6ac44
If WQE ID is used in CQE for Multi-Packet RQ, the ratio of CQE compression drops a little bit. In order to reach to 100Gbps with 64B traffic, it is needed to further save PCIe bandwidth by increasing the number of strides in a WQE. It is now 64 by default but adjustable by a PMD parameter - mprq_log_stride_num. Signed-off-by: Yongseok Koh <yskoh@mellanox.com> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_DEFS_H_
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#define RTE_PMD_MLX5_DEFS_H_
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#include <rte_ethdev_driver.h>
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#include "mlx5_autoconf.h"
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/* Reported driver name. */
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#define MLX5_DRIVER_NAME "net_mlx5"
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/* Maximum number of simultaneous unicast MAC addresses. */
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#define MLX5_MAX_UC_MAC_ADDRESSES 128
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/* Maximum number of simultaneous Multicast MAC addresses. */
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#define MLX5_MAX_MC_MAC_ADDRESSES 128
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/* Maximum number of simultaneous MAC addresses. */
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#define MLX5_MAX_MAC_ADDRESSES \
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(MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
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/* Maximum number of simultaneous VLAN filters. */
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#define MLX5_MAX_VLAN_IDS 128
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/*
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* Request TX completion every time descriptors reach this threshold since
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* the previous request. Must be a power of two for performance reasons.
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*/
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#define MLX5_TX_COMP_THRESH 32
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/*
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* Request TX completion every time the total number of WQEBBs used for inlining
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* packets exceeds the size of WQ divided by this divisor. Better to be power of
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* two for performance.
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*/
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#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
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/* Size of per-queue MR cache array for linear search. */
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#define MLX5_MR_CACHE_N 8
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/* Size of MR cache table for binary search. */
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#define MLX5_MR_BTREE_CACHE_N 256
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/*
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* If defined, only use software counters. The PMD will never ask the hardware
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* for these, and many of them won't be available.
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*/
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#ifndef MLX5_PMD_SOFT_COUNTERS
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#define MLX5_PMD_SOFT_COUNTERS 1
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#endif
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/* Alarm timeout. */
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#define MLX5_ALARM_TIMEOUT_US 100000
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/* Maximum number of extended statistics counters. */
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#define MLX5_MAX_XSTATS 32
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/* Maximum Packet headers size (L2+L3+L4) for TSO. */
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#define MLX5_MAX_TSO_HEADER 192
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/* Default minimum number of Tx queues for vectorized Tx. */
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#define MLX5_VPMD_MIN_TXQS 4
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/* Threshold of buffer replenishment for vectorized Rx. */
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#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
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(RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
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/* Maximum size of burst for vectorized Rx. */
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#define MLX5_VPMD_RX_MAX_BURST 64U
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/*
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* Maximum size of burst for vectorized Tx. This is related to the maximum size
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* of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW.
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* Careful when changing, large value can cause WQE DS to overlap.
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*/
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#define MLX5_VPMD_TX_MAX_BURST 32U
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/* Number of packets vectorized Rx can simultaneously process in a loop. */
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#define MLX5_VPMD_DESCS_PER_LOOP 4
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/* Supported RSS */
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#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
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/* Timeout in seconds to get a valid link status. */
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#define MLX5_LINK_STATUS_TIMEOUT 10
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/* Reserved address space for UAR mapping. */
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#define MLX5_UAR_SIZE (1ULL << 32)
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/* Offset of reserved UAR address space to hugepage memory. Offset is used here
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* to minimize possibility of address next to hugepage being used by other code
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* in either primary or secondary process, failing to map TX UAR would make TX
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* packets invisible to HW.
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*/
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#define MLX5_UAR_OFFSET (1ULL << 32)
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/* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
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#define MLX5_MPRQ_STRIDE_NUM_N 6U
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/* Two-byte shift is disabled for Multi-Packet RQ. */
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#define MLX5_MPRQ_TWO_BYTE_SHIFT 0
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/*
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* Minimum size of packet to be memcpy'd instead of being attached as an
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* external buffer.
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*/
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#define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
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/* Minimum number Rx queues to enable Multi-Packet RQ. */
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#define MLX5_MPRQ_MIN_RXQS 12
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/* Cache size of mempool for Multi-Packet RQ. */
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#define MLX5_MPRQ_MP_CACHE_SZ 32
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#endif /* RTE_PMD_MLX5_DEFS_H_ */
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