936eda25e8
This patch adds get_reg related function codes for hns3 PMD driver. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Chunsong Feng <fengchunsong@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Signed-off-by: Hao Chen <chenhao164@huawei.com> Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_REGS_H_
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#define _HNS3_REGS_H_
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/* bar registers for cmdq */
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#define HNS3_CMDQ_TX_ADDR_L_REG 0x27000
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#define HNS3_CMDQ_TX_ADDR_H_REG 0x27004
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#define HNS3_CMDQ_TX_DEPTH_REG 0x27008
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#define HNS3_CMDQ_TX_TAIL_REG 0x27010
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#define HNS3_CMDQ_TX_HEAD_REG 0x27014
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#define HNS3_CMDQ_RX_ADDR_L_REG 0x27018
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#define HNS3_CMDQ_RX_ADDR_H_REG 0x2701c
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#define HNS3_CMDQ_RX_DEPTH_REG 0x27020
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#define HNS3_CMDQ_RX_TAIL_REG 0x27024
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#define HNS3_CMDQ_RX_HEAD_REG 0x27028
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#define HNS3_CMDQ_INTR_STS_REG 0x27104
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#define HNS3_CMDQ_INTR_EN_REG 0x27108
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#define HNS3_CMDQ_INTR_GEN_REG 0x2710C
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HNS3_VECTOR0_CMDQ_SRC_REG 0x27100
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/* Vector0 interrupt CMDQ event status register(RO) */
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#define HNS3_VECTOR0_CMDQ_STAT_REG 0x27104
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#define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
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#define HNS3_MISC_VECTOR_REG_BASE 0x20400
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#define HNS3_VECTOR0_OTER_EN_REG 0x20600
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#define HNS3_MISC_RESET_STS_REG 0x20700
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#define HNS3_GLOBAL_RESET_REG 0x20A00
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#define HNS3_FUN_RST_ING 0x20C00
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#define HNS3_GRO_EN_REG 0x28000
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/* Vector0 register bits for reset */
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#define HNS3_VECTOR0_FUNCRESET_INT_B 0
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#define HNS3_VECTOR0_GLOBALRESET_INT_B 5
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#define HNS3_VECTOR0_CORERESET_INT_B 6
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#define HNS3_VECTOR0_IMPRESET_INT_B 7
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/* CMDQ register bits for RX event(=MBX event) */
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#define HNS3_VECTOR0_RX_CMDQ_INT_B 1
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#define HNS3_VECTOR0_REG_MSIX_MASK 0x1FF00
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/* RST register bits for RESET event */
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#define HNS3_VECTOR0_RST_INT_B 2
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#define HNS3_VF_RST_ING 0x07008
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#define HNS3_VF_RST_ING_BIT BIT(16)
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/* bar registers for rcb */
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#define HNS3_RING_RX_BASEADDR_L_REG 0x00000
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#define HNS3_RING_RX_BASEADDR_H_REG 0x00004
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#define HNS3_RING_RX_BD_NUM_REG 0x00008
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#define HNS3_RING_RX_BD_LEN_REG 0x0000C
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#define HNS3_RING_RX_MERGE_EN_REG 0x00014
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#define HNS3_RING_RX_TAIL_REG 0x00018
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#define HNS3_RING_RX_HEAD_REG 0x0001C
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#define HNS3_RING_RX_FBDNUM_REG 0x00020
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#define HNS3_RING_RX_OFFSET_REG 0x00024
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#define HNS3_RING_RX_FBD_OFFSET_REG 0x00028
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#define HNS3_RING_RX_PKTNUM_RECORD_REG 0x0002C
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#define HNS3_RING_RX_STASH_REG 0x00030
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#define HNS3_RING_RX_BD_ERR_REG 0x00034
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#define HNS3_RING_TX_BASEADDR_L_REG 0x00040
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#define HNS3_RING_TX_BASEADDR_H_REG 0x00044
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#define HNS3_RING_TX_BD_NUM_REG 0x00048
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#define HNS3_RING_TX_PRIORITY_REG 0x0004C
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#define HNS3_RING_TX_TC_REG 0x00050
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#define HNS3_RING_TX_MERGE_EN_REG 0x00054
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#define HNS3_RING_TX_TAIL_REG 0x00058
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#define HNS3_RING_TX_HEAD_REG 0x0005C
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#define HNS3_RING_TX_FBDNUM_REG 0x00060
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#define HNS3_RING_TX_OFFSET_REG 0x00064
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#define HNS3_RING_TX_EBD_NUM_REG 0x00068
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#define HNS3_RING_TX_PKTNUM_RECORD_REG 0x0006C
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#define HNS3_RING_TX_EBD_OFFSET_REG 0x00070
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#define HNS3_RING_TX_BD_ERR_REG 0x00074
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#define HNS3_RING_EN_REG 0x00090
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#define HNS3_RING_EN_B 0
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#define HNS3_TQP_REG_OFFSET 0x80000
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#define HNS3_TQP_REG_SIZE 0x200
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/* bar registers for tqp interrupt */
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#define HNS3_TQP_INTR_CTRL_REG 0x20000
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#define HNS3_TQP_INTR_GL0_REG 0x20100
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#define HNS3_TQP_INTR_GL1_REG 0x20200
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#define HNS3_TQP_INTR_GL2_REG 0x20300
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#define HNS3_TQP_INTR_RL_REG 0x20900
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#define HNS3_TQP_INTR_REG_SIZE 4
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int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs);
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#endif /* _HNS3_REGS_H_ */
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