7be78d0279
The tool comes from https://github.com/jsoref Signed-off-by: Josh Soref <jsoref@gmail.com> Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2019-2021 Xilinx, Inc.
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* Copyright(c) 2018-2019 Solarflare Communications Inc.
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*
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* This software was jointly developed between OKTET Labs (under contract
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* for Solarflare) and Solarflare Communications, Inc.
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*/
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#ifndef _SFC_EF100_H
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#define _SFC_EF100_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Prime event queue to allow processed events to be reused.
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*
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* @param evq_prime Global address of the prime register
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* @param evq_hw_index Event queue index
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* @param evq_read_ptr Masked event queue read pointer
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*/
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static inline void
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sfc_ef100_evq_prime(volatile void *evq_prime, unsigned int evq_hw_index,
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unsigned int evq_read_ptr)
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{
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efx_dword_t dword;
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EFX_POPULATE_DWORD_2(dword,
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ERF_GZ_EVQ_ID, evq_hw_index,
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ERF_GZ_IDX, evq_read_ptr);
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/*
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* EvQ prime on EF100 allows HW to reuse descriptors. So we
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* should be sure that event descriptor reads are done.
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* However, there is implicit data dependency here since we
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* move past event if we have found out that the event has
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* come (i.e. we read it) and we have processed it.
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* So, no extra barriers are required here.
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*/
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rte_write32_relaxed(dword.ed_u32[0], evq_prime);
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}
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static inline bool
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sfc_ef100_ev_present(const efx_qword_t *ev, bool phase_bit)
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{
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return !((ev->eq_u64[0] &
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EFX_INPLACE_MASK64(0, 63, ESF_GZ_EV_EVQ_PHASE)) ^
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((uint64_t)phase_bit << ESF_GZ_EV_EVQ_PHASE_LBN));
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}
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static inline bool
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sfc_ef100_ev_type_is(const efx_qword_t *ev, unsigned int type)
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{
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return (ev->eq_u64[0] & EFX_INPLACE_MASK64(0, 63, ESF_GZ_E_TYPE)) ==
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EFX_INSERT_FIELD64(0, 63, ESF_GZ_E_TYPE, type);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SFC_EF100_H */
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