17424ededb
Add function to cancel event timer that has been armed. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
210 lines
6.2 KiB
C
210 lines
6.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_TIM_EVDEV_H__
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#define __OTX2_TIM_EVDEV_H__
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#include <rte_event_timer_adapter.h>
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#include <rte_event_timer_adapter_pmd.h>
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#include <rte_reciprocal.h>
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#include "otx2_dev.h"
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#define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
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#define otx2_tim_func_trace otx2_tim_dbg
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#define TIM_LF_RING_AURA (0x0)
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#define TIM_LF_RING_BASE (0x130)
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#define TIM_LF_NRSPERR_INT (0x200)
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#define TIM_LF_NRSPERR_INT_W1S (0x208)
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#define TIM_LF_NRSPERR_INT_ENA_W1S (0x210)
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#define TIM_LF_NRSPERR_INT_ENA_W1C (0x218)
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#define TIM_LF_RAS_INT (0x300)
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#define TIM_LF_RAS_INT_W1S (0x308)
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#define TIM_LF_RAS_INT_ENA_W1S (0x310)
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#define TIM_LF_RAS_INT_ENA_W1C (0x318)
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#define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
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#define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ULL << (64 - \
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TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
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#define TIM_BUCKET_W1_S_LOCK (40)
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#define TIM_BUCKET_W1_M_LOCK ((1ULL << \
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(TIM_BUCKET_W1_S_CHUNK_REMAINDER - \
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TIM_BUCKET_W1_S_LOCK)) - 1)
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#define TIM_BUCKET_W1_S_RSVD (35)
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#define TIM_BUCKET_W1_S_BSK (34)
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#define TIM_BUCKET_W1_M_BSK ((1ULL << \
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(TIM_BUCKET_W1_S_RSVD - \
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TIM_BUCKET_W1_S_BSK)) - 1)
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#define TIM_BUCKET_W1_S_HBT (33)
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#define TIM_BUCKET_W1_M_HBT ((1ULL << \
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(TIM_BUCKET_W1_S_BSK - \
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TIM_BUCKET_W1_S_HBT)) - 1)
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#define TIM_BUCKET_W1_S_SBT (32)
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#define TIM_BUCKET_W1_M_SBT ((1ULL << \
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(TIM_BUCKET_W1_S_HBT - \
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TIM_BUCKET_W1_S_SBT)) - 1)
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#define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
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#define TIM_BUCKET_W1_M_NUM_ENTRIES ((1ULL << \
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(TIM_BUCKET_W1_S_SBT - \
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TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
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#define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
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#define TIM_BUCKET_CHUNK_REMAIN \
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(TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
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#define TIM_BUCKET_LOCK \
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(TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
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#define TIM_BUCKET_SEMA_WLOCK \
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(TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
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#define OTX2_MAX_TIM_RINGS (256)
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#define OTX2_TIM_MAX_BUCKETS (0xFFFFF)
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#define OTX2_TIM_RING_DEF_CHUNK_SZ (4096)
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#define OTX2_TIM_CHUNK_ALIGNMENT (16)
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#define OTX2_TIM_MAX_BURST (RTE_CACHE_LINE_SIZE / \
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OTX2_TIM_CHUNK_ALIGNMENT)
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#define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
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#define OTX2_TIM_MIN_CHUNK_SLOTS (0x1)
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#define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE)
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#define OTX2_TIM_MIN_TMO_TKS (256)
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#define OTX2_TIM_SP 0x1
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#define OTX2_TIM_MP 0x2
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#define OTX2_TIM_BKT_AND 0x4
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#define OTX2_TIM_BKT_MOD 0x8
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#define OTX2_TIM_ENA_FB 0x10
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#define OTX2_TIM_ENA_DFB 0x20
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enum otx2_tim_clk_src {
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OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
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OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
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OTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
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OTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
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};
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struct otx2_tim_bkt {
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uint64_t first_chunk;
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union {
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uint64_t w1;
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struct {
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uint32_t nb_entry;
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uint8_t sbt:1;
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uint8_t hbt:1;
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uint8_t bsk:1;
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uint8_t rsvd:5;
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uint8_t lock;
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int16_t chunk_remainder;
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};
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};
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uint64_t current_chunk;
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uint64_t pad;
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} __rte_packed __rte_aligned(32);
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struct otx2_tim_ent {
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uint64_t w0;
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uint64_t wqe;
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} __rte_packed;
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struct otx2_tim_evdev {
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struct rte_pci_device *pci_dev;
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struct rte_eventdev *event_dev;
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struct otx2_mbox *mbox;
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uint16_t nb_rings;
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uint32_t chunk_sz;
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uintptr_t bar2;
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/* Dev args */
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uint8_t disable_npa;
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uint16_t chunk_slots;
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/* MSIX offsets */
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uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];
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};
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struct otx2_tim_ring {
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uintptr_t base;
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struct rte_reciprocal_u64 fast_div;
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uint16_t nb_chunk_slots;
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uint32_t nb_bkts;
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uint64_t ring_start_cyc;
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struct otx2_tim_bkt *bkt;
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struct rte_mempool *chunk_pool;
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uint64_t tck_int;
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uint8_t prod_type_sp;
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uint8_t disable_npa;
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uint8_t optimized;
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uint8_t ena_dfb;
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uint16_t ring_id;
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uint32_t aura;
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uint64_t tck_nsec;
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uint64_t max_tout;
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uint64_t nb_chunks;
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uint64_t chunk_sz;
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uint64_t tenns_clk_freq;
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enum otx2_tim_clk_src clk_src;
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} __rte_cache_aligned;
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static inline struct otx2_tim_evdev *
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tim_priv_get(void)
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{
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const struct rte_memzone *mz;
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mz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));
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if (mz == NULL)
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return NULL;
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return mz->addr;
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}
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#define TIM_ARM_FASTPATH_MODES \
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FP(mod_sp, 0, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
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FP(mod_mp, 0, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
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FP(mod_fb_sp, 0, 1, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
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FP(mod_fb_mp, 0, 1, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
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FP(and_sp, 1, 0, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
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FP(and_mp, 1, 0, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
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FP(and_fb_sp, 1, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
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FP(and_fb_mp, 1, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
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#define FP(_name, _f3, _f2, _f1, flags) \
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uint16_t otx2_tim_arm_burst_ ## _name( \
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const struct rte_event_timer_adapter *adptr, \
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struct rte_event_timer **tim, \
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const uint16_t nb_timers);
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TIM_ARM_FASTPATH_MODES
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#undef FP
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#define TIM_ARM_TMO_FASTPATH_MODES \
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FP(mod, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB) \
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FP(mod_fb, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB) \
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FP(and, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB) \
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FP(and_fb, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB) \
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#define FP(_name, _f2, _f1, flags) \
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uint16_t otx2_tim_arm_tmo_tick_burst_ ## _name( \
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const struct rte_event_timer_adapter *adptr, \
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struct rte_event_timer **tim, \
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const uint64_t timeout_tick, const uint16_t nb_timers);
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TIM_ARM_TMO_FASTPATH_MODES
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#undef FP
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uint16_t otx2_tim_timer_cancel_burst(
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const struct rte_event_timer_adapter *adptr,
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struct rte_event_timer **tim, const uint16_t nb_timers);
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int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
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uint32_t *caps,
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const struct rte_event_timer_adapter_ops **ops);
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void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
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void otx2_tim_fini(void);
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/* TIM IRQ */
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int tim_register_irq(uint16_t ring_id);
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void tim_unregister_irq(uint16_t ring_id);
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#endif /* __OTX2_TIM_EVDEV_H__ */
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