df6e0a06a3
Renamed data type from phys_addr_t to rte_iova_t. Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Reviewed-by: Anatoly Burakov <anatoly.burakov@intel.com> Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
178 lines
5.6 KiB
C
178 lines
5.6 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2015-2017 Atomic Rules LLC
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARK_DDM_H_
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#define _ARK_DDM_H_
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#include <stdint.h>
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#include <rte_memory.h>
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/* The DDM or Downstream Data Mover is an internal Arkville hardware
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* module for moving packet from host memory to the TX packet streams.
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* This module is *not* intended for end-user manipulation, hence
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* there is minimal documentation.
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*/
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/* struct defining Tx meta data -- fixed in FPGA -- 16 bytes */
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struct ark_tx_meta {
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uint64_t physaddr;
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uint32_t delta_ns;
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uint16_t data_len; /* of this MBUF */
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#define ARK_DDM_EOP 0x01
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#define ARK_DDM_SOP 0x02
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uint8_t flags; /* bit 0 indicates last mbuf in chain. */
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uint8_t reserved[1];
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};
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/*
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* DDM core hardware structures
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* These are overlay structures to a memory mapped FPGA device. These
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* structs will never be instantiated in ram memory
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*/
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#define ARK_DDM_CFG 0x0000
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#define ARK_DDM_CONST 0xfacecafe
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struct ark_ddm_cfg_t {
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uint32_t r0;
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volatile uint32_t tlp_stats_clear;
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uint32_t const0;
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volatile uint32_t tag_max;
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volatile uint32_t command;
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volatile uint32_t stop_flushed;
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};
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#define ARK_DDM_STATS 0x0020
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struct ark_ddm_stats_t {
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volatile uint64_t tx_byte_count;
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volatile uint64_t tx_pkt_count;
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volatile uint64_t tx_mbuf_count;
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};
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#define ARK_DDM_MRDQ 0x0040
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struct ark_ddm_mrdq_t {
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volatile uint32_t mrd_q1;
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volatile uint32_t mrd_q2;
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volatile uint32_t mrd_q3;
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volatile uint32_t mrd_q4;
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volatile uint32_t mrd_full;
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};
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#define ARK_DDM_CPLDQ 0x0068
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struct ark_ddm_cpldq_t {
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volatile uint32_t cpld_q1;
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volatile uint32_t cpld_q2;
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volatile uint32_t cpld_q3;
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volatile uint32_t cpld_q4;
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volatile uint32_t cpld_full;
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};
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#define ARK_DDM_MRD_PS 0x0090
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struct ark_ddm_mrd_ps_t {
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volatile uint32_t mrd_ps_min;
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volatile uint32_t mrd_ps_max;
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volatile uint32_t mrd_full_ps_min;
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volatile uint32_t mrd_full_ps_max;
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volatile uint32_t mrd_dw_ps_min;
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volatile uint32_t mrd_dw_ps_max;
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};
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#define ARK_DDM_QUEUE_STATS 0x00a8
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struct ark_ddm_qstats_t {
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volatile uint64_t byte_count;
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volatile uint64_t pkt_count;
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volatile uint64_t mbuf_count;
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};
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#define ARK_DDM_CPLD_PS 0x00c0
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struct ark_ddm_cpld_ps_t {
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volatile uint32_t cpld_ps_min;
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volatile uint32_t cpld_ps_max;
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volatile uint32_t cpld_full_ps_min;
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volatile uint32_t cpld_full_ps_max;
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volatile uint32_t cpld_dw_ps_min;
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volatile uint32_t cpld_dw_ps_max;
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};
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#define ARK_DDM_SETUP 0x00e0
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struct ark_ddm_setup_t {
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rte_iova_t cons_write_index_addr;
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uint32_t write_index_interval; /* 4ns each */
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volatile uint32_t cons_index;
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};
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#define ARK_DDM_EXPECTED_SIZE 256
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#define ARK_DDM_QOFFSET ARK_DDM_EXPECTED_SIZE
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/* Consolidated structure */
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struct ark_ddm_t {
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struct ark_ddm_cfg_t cfg;
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uint8_t reserved0[(ARK_DDM_STATS - ARK_DDM_CFG) -
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sizeof(struct ark_ddm_cfg_t)];
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struct ark_ddm_stats_t stats;
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uint8_t reserved1[(ARK_DDM_MRDQ - ARK_DDM_STATS) -
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sizeof(struct ark_ddm_stats_t)];
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struct ark_ddm_mrdq_t mrdq;
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uint8_t reserved2[(ARK_DDM_CPLDQ - ARK_DDM_MRDQ) -
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sizeof(struct ark_ddm_mrdq_t)];
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struct ark_ddm_cpldq_t cpldq;
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uint8_t reserved3[(ARK_DDM_MRD_PS - ARK_DDM_CPLDQ) -
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sizeof(struct ark_ddm_cpldq_t)];
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struct ark_ddm_mrd_ps_t mrd_ps;
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struct ark_ddm_qstats_t queue_stats;
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struct ark_ddm_cpld_ps_t cpld_ps;
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uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_CPLD_PS) -
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sizeof(struct ark_ddm_cpld_ps_t)];
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struct ark_ddm_setup_t setup;
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uint8_t reserved_p[(ARK_DDM_EXPECTED_SIZE - ARK_DDM_SETUP) -
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sizeof(struct ark_ddm_setup_t)];
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};
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/* DDM function prototype */
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int ark_ddm_verify(struct ark_ddm_t *ddm);
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void ark_ddm_start(struct ark_ddm_t *ddm);
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int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait);
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void ark_ddm_reset(struct ark_ddm_t *ddm);
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void ark_ddm_stats_reset(struct ark_ddm_t *ddm);
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void ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr,
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uint32_t interval);
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void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg);
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void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg);
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int ark_ddm_is_stopped(struct ark_ddm_t *ddm);
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uint64_t ark_ddm_queue_byte_count(struct ark_ddm_t *ddm);
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uint64_t ark_ddm_queue_pkt_count(struct ark_ddm_t *ddm);
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void ark_ddm_queue_reset_stats(struct ark_ddm_t *ddm);
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#endif
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