fcee050aa1
NXP Copyright has been wrongly worded with '(c)' at various places. This patch removes these extra characters. It also removes "All rights reserved". Only NXP copyright syntax is changed. Freescale copyright is not modified. Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
257 lines
11 KiB
C
257 lines
11 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* BSD LICENSE
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*
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* Copyright 2013-2016 Freescale Semiconductor Inc.
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* Copyright 2016 NXP.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* GPL LICENSE SUMMARY
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_DPSECI_CMD_H
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#define _FSL_DPSECI_CMD_H
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/* DPSECI Version */
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#define DPSECI_VER_MAJOR 5
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#define DPSECI_VER_MINOR 0
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/* Command IDs */
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#define DPSECI_CMDID_CLOSE ((0x800 << 4) | (0x1))
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#define DPSECI_CMDID_OPEN ((0x809 << 4) | (0x1))
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#define DPSECI_CMDID_CREATE ((0x909 << 4) | (0x1))
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#define DPSECI_CMDID_DESTROY ((0x989 << 4) | (0x1))
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#define DPSECI_CMDID_GET_API_VERSION ((0xa09 << 4) | (0x1))
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#define DPSECI_CMDID_ENABLE ((0x002 << 4) | (0x1))
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#define DPSECI_CMDID_DISABLE ((0x003 << 4) | (0x1))
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#define DPSECI_CMDID_GET_ATTR ((0x004 << 4) | (0x1))
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#define DPSECI_CMDID_RESET ((0x005 << 4) | (0x1))
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#define DPSECI_CMDID_IS_ENABLED ((0x006 << 4) | (0x1))
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#define DPSECI_CMDID_SET_IRQ ((0x010 << 4) | (0x1))
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#define DPSECI_CMDID_GET_IRQ ((0x011 << 4) | (0x1))
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#define DPSECI_CMDID_SET_IRQ_ENABLE ((0x012 << 4) | (0x1))
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#define DPSECI_CMDID_GET_IRQ_ENABLE ((0x013 << 4) | (0x1))
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#define DPSECI_CMDID_SET_IRQ_MASK ((0x014 << 4) | (0x1))
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#define DPSECI_CMDID_GET_IRQ_MASK ((0x015 << 4) | (0x1))
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#define DPSECI_CMDID_GET_IRQ_STATUS ((0x016 << 4) | (0x1))
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#define DPSECI_CMDID_CLEAR_IRQ_STATUS ((0x017 << 4) | (0x1))
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#define DPSECI_CMDID_SET_RX_QUEUE ((0x194 << 4) | (0x1))
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#define DPSECI_CMDID_GET_RX_QUEUE ((0x196 << 4) | (0x1))
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#define DPSECI_CMDID_GET_TX_QUEUE ((0x197 << 4) | (0x1))
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#define DPSECI_CMDID_GET_SEC_ATTR ((0x198 << 4) | (0x1))
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#define DPSECI_CMDID_GET_SEC_COUNTERS ((0x199 << 4) | (0x1))
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_OPEN(cmd, dpseci_id) \
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MC_CMD_OP(cmd, 0, 0, 32, int, dpseci_id)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_CREATE(cmd, cfg) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->priorities[0]);\
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MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->priorities[1]);\
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MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priorities[2]);\
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MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->priorities[3]);\
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priorities[4]);\
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MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->priorities[5]);\
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MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->priorities[6]);\
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MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->priorities[7]);\
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MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->num_tx_queues);\
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MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->num_rx_queues);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_IS_ENABLED(cmd, en) \
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MC_RSP_OP(cmd, 0, 0, 1, int, en)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
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MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
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MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
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MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_IRQ(cmd, irq_index) \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_IRQ(cmd, type, irq_cfg) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
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MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
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MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
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MC_RSP_OP(cmd, 2, 32, 32, int, type); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
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MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_IRQ_MASK(cmd, irq_index) \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_IRQ_MASK(cmd, mask) \
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MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_IRQ_STATUS(cmd, status) \
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MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_ATTR(cmd, attr) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 32, int, attr->id); \
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MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_tx_queues); \
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MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->num_rx_queues); \
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg) \
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do { \
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MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
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MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \
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MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue); \
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MC_CMD_OP(cmd, 0, 48, 4, enum dpseci_dest, cfg->dest_cfg.dest_type); \
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MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
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MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
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MC_CMD_OP(cmd, 2, 32, 1, int, cfg->order_preservation_en);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_RX_QUEUE(cmd, queue) \
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MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_RX_QUEUE(cmd, attr) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
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MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
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MC_RSP_OP(cmd, 0, 48, 4, enum dpseci_dest, attr->dest_cfg.dest_type);\
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MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
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MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
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MC_RSP_OP(cmd, 2, 32, 1, int, attr->order_preservation_en);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_CMD_GET_TX_QUEUE(cmd, queue) \
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MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_TX_QUEUE(cmd, attr) \
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do { \
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MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid);\
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MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->priority);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_SEC_ATTR(cmd, attr) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->ip_id);\
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MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->major_rev);\
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MC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->minor_rev);\
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MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->era);\
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MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->deco_num);\
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MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->zuc_auth_acc_num);\
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MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->zuc_enc_acc_num);\
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MC_RSP_OP(cmd, 1, 32, 8, uint8_t, attr->snow_f8_acc_num);\
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MC_RSP_OP(cmd, 1, 40, 8, uint8_t, attr->snow_f9_acc_num);\
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MC_RSP_OP(cmd, 1, 48, 8, uint8_t, attr->crc_acc_num);\
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MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->pk_acc_num);\
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MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->kasumi_acc_num);\
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MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->rng_acc_num);\
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MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->md_acc_num);\
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MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->arc4_acc_num);\
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MC_RSP_OP(cmd, 2, 48, 8, uint8_t, attr->des_acc_num);\
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MC_RSP_OP(cmd, 2, 56, 8, uint8_t, attr->aes_acc_num);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_SEC_COUNTERS(cmd, counters) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 64, uint64_t, counters->dequeued_requests);\
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MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counters->ob_enc_requests);\
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MC_RSP_OP(cmd, 2, 0, 64, uint64_t, counters->ib_dec_requests);\
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MC_RSP_OP(cmd, 3, 0, 64, uint64_t, counters->ob_enc_bytes);\
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MC_RSP_OP(cmd, 4, 0, 64, uint64_t, counters->ob_prot_bytes);\
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MC_RSP_OP(cmd, 5, 0, 64, uint64_t, counters->ib_dec_bytes);\
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MC_RSP_OP(cmd, 6, 0, 64, uint64_t, counters->ib_valid_bytes);\
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} while (0)
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/* cmd, param, offset, width, type, arg_name */
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#define DPSECI_RSP_GET_API_VERSION(cmd, major, minor) \
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do { \
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MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
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MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
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} while (0)
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#endif /* _FSL_DPSECI_CMD_H */
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