Pavan Nikhilesh 3e97fa671d config: align mempool elements to 128 bytes on CN10K ... Mempool elements are by default aligned to CACHELINE_SIZE. In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to 128B. Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned 128 bytes. Fixes: 1b4c86a721 ("config/arm: add Marvell CN10K") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>		2022-02-12 15:13:24 +01:00
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arm	config: align mempool elements to 128 bytes on CN10K	2022-02-12 15:13:24 +01:00
ppc	ci: add ppc64le cross compilation in GHA	2021-11-10 11:48:01 +01:00
x86	build: fix warnings when running external commands	2022-02-02 15:44:12 +01:00
meson.build	build: fix warning about using -Wextra flag	2022-02-02 15:56:45 +01:00
rte_config.h	kni: allow configuring thread granularity	2022-02-02 20:45:18 +01:00