4ffd224742
Add data structures required for the data path of IOAT devices. Signed-off-by: Conor Walsh <conor.walsh@intel.com> Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Kevin Laatz <kevin.laatz@intel.com>
296 lines
6.7 KiB
C
296 lines
6.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 Intel Corporation
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*/
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#ifndef IOAT_HW_DEFS_H
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#define IOAT_HW_DEFS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#define IOAT_PCI_CHANERR_INT_OFFSET 0x180
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#define IOAT_VER_3_0 0x30
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#define IOAT_VER_3_3 0x33
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#define IOAT_VER_3_4 0x34
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#define IOAT_VENDOR_ID 0x8086
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#define IOAT_DEVICE_ID_SKX 0x2021
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#define IOAT_DEVICE_ID_BDX0 0x6f20
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#define IOAT_DEVICE_ID_BDX1 0x6f21
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#define IOAT_DEVICE_ID_BDX2 0x6f22
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#define IOAT_DEVICE_ID_BDX3 0x6f23
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#define IOAT_DEVICE_ID_BDX4 0x6f24
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#define IOAT_DEVICE_ID_BDX5 0x6f25
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#define IOAT_DEVICE_ID_BDX6 0x6f26
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#define IOAT_DEVICE_ID_BDX7 0x6f27
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#define IOAT_DEVICE_ID_BDXE 0x6f2E
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#define IOAT_DEVICE_ID_BDXF 0x6f2F
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#define IOAT_DEVICE_ID_ICX 0x0b00
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#define IOAT_COMP_UPDATE_SHIFT 3
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#define IOAT_CMD_OP_SHIFT 24
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/* DMA Channel Registers */
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#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
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#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
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#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
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#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_INT_REARM 0x0001
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/* DMA Channel Capabilities */
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#define IOAT_DMACAP_PB (1 << 0)
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#define IOAT_DMACAP_DCA (1 << 4)
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#define IOAT_DMACAP_BFILL (1 << 6)
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#define IOAT_DMACAP_XOR (1 << 8)
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#define IOAT_DMACAP_PQ (1 << 9)
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#define IOAT_DMACAP_DMA_DIF (1 << 10)
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struct ioat_registers {
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uint8_t chancnt;
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uint8_t xfercap;
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uint8_t genctrl;
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uint8_t intrctrl;
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uint32_t attnstatus;
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uint8_t cbver; /* 0x08 */
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uint8_t reserved4[0x3]; /* 0x09 */
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uint16_t intrdelay; /* 0x0C */
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uint16_t cs_status; /* 0x0E */
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uint32_t dmacapability; /* 0x10 */
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uint8_t reserved5[0x6C]; /* 0x14 */
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uint16_t chanctrl; /* 0x80 */
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uint8_t reserved6[0x2]; /* 0x82 */
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uint8_t chancmd; /* 0x84 */
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uint8_t reserved3[1]; /* 0x85 */
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uint16_t dmacount; /* 0x86 */
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uint64_t chansts; /* 0x88 */
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uint64_t chainaddr; /* 0x90 */
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uint64_t chancmp; /* 0x98 */
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uint8_t reserved2[0x8]; /* 0xA0 */
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uint32_t chanerr; /* 0xA8 */
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uint32_t chanerrmask; /* 0xAC */
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} __rte_packed;
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#define IOAT_CHANCMD_RESET 0x20
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#define IOAT_CHANCMD_SUSPEND 0x04
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#define IOAT_CHANSTS_STATUS 0x7ULL
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#define IOAT_CHANSTS_ACTIVE 0x0
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#define IOAT_CHANSTS_IDLE 0x1
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#define IOAT_CHANSTS_SUSPENDED 0x2
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#define IOAT_CHANSTS_HALTED 0x3
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#define IOAT_CHANSTS_ARMED 0x4
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#define IOAT_CHANERR_INVALID_SRC_ADDR_MASK (1 << 0)
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#define IOAT_CHANERR_INVALID_DST_ADDR_MASK (1 << 1)
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#define IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK (1 << 8)
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#define IOAT_CHANERR_INVALID_LENGTH_MASK (1 << 10)
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const char *chansts_readable[] = {
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"ACTIVE", /* 0x0 */
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"IDLE", /* 0x1 */
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"SUSPENDED", /* 0x2 */
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"HALTED", /* 0x3 */
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"ARMED" /* 0x4 */
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};
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#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
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#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL
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#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
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#define IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */
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struct ioat_dma_hw_desc {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct {
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uint32_t int_enable: 1;
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uint32_t src_snoop_disable: 1;
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uint32_t dest_snoop_disable: 1;
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uint32_t completion_update: 1;
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uint32_t fence: 1;
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uint32_t null: 1;
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uint32_t src_page_break: 1;
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uint32_t dest_page_break: 1;
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uint32_t bundle: 1;
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uint32_t dest_dca: 1;
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uint32_t hint: 1;
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uint32_t reserved: 13;
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#define IOAT_OP_COPY 0x00
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uint32_t op: 8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t reserved;
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uint64_t reserved2;
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uint64_t user1;
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uint64_t user2;
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};
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struct ioat_fill_hw_desc {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct {
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uint32_t int_enable: 1;
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uint32_t reserved: 1;
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uint32_t dest_snoop_disable: 1;
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uint32_t completion_update: 1;
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uint32_t fence: 1;
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uint32_t reserved2: 2;
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uint32_t dest_page_break: 1;
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uint32_t bundle: 1;
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uint32_t reserved3: 15;
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#define IOAT_OP_FILL 0x01
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uint32_t op: 8;
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} control;
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} u;
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uint64_t src_data;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t reserved;
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uint64_t next_dest_addr;
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uint64_t user1;
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uint64_t user2;
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};
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struct ioat_xor_hw_desc {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct {
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uint32_t int_enable: 1;
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uint32_t src_snoop_disable: 1;
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uint32_t dest_snoop_disable: 1;
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uint32_t completion_update: 1;
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uint32_t fence: 1;
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uint32_t src_count: 3;
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uint32_t bundle: 1;
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uint32_t dest_dca: 1;
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uint32_t hint: 1;
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uint32_t reserved: 13;
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#define IOAT_OP_XOR 0x87
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#define IOAT_OP_XOR_VAL 0x88
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uint32_t op: 8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint64_t src_addr4;
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uint64_t src_addr5;
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};
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struct ioat_xor_ext_hw_desc {
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uint64_t src_addr6;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t next;
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uint64_t reserved[4];
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};
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struct ioat_pq_hw_desc {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct {
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uint32_t int_enable: 1;
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uint32_t src_snoop_disable: 1;
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uint32_t dest_snoop_disable: 1;
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uint32_t completion_update: 1;
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uint32_t fence: 1;
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uint32_t src_count: 3;
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uint32_t bundle: 1;
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uint32_t dest_dca: 1;
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uint32_t hint: 1;
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uint32_t p_disable: 1;
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uint32_t q_disable: 1;
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uint32_t reserved: 11;
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#define IOAT_OP_PQ 0x89
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#define IOAT_OP_PQ_VAL 0x8a
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uint32_t op: 8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint8_t coef[8];
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uint64_t q_addr;
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};
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struct ioat_pq_ext_hw_desc {
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uint64_t src_addr4;
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uint64_t src_addr5;
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uint64_t src_addr6;
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uint64_t next;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t reserved[2];
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};
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struct ioat_pq_update_hw_desc {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct {
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uint32_t int_enable: 1;
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uint32_t src_snoop_disable: 1;
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uint32_t dest_snoop_disable: 1;
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uint32_t completion_update: 1;
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uint32_t fence: 1;
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uint32_t src_cnt: 3;
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uint32_t bundle: 1;
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uint32_t dest_dca: 1;
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uint32_t hint: 1;
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uint32_t p_disable: 1;
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uint32_t q_disable: 1;
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uint32_t reserved: 3;
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uint32_t coef: 8;
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#define IOAT_OP_PQ_UP 0x8b
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uint32_t op: 8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t p_src;
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uint64_t q_src;
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uint64_t q_addr;
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};
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union ioat_hw_desc {
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struct ioat_dma_hw_desc dma;
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struct ioat_fill_hw_desc fill;
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struct ioat_xor_hw_desc xor_desc;
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struct ioat_xor_ext_hw_desc xor_ext;
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struct ioat_pq_hw_desc pq;
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struct ioat_pq_ext_hw_desc pq_ext;
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struct ioat_pq_update_hw_desc pq_update;
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};
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#define GENSTS_DEV_STATE_MASK 0x03
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#define CMDSTATUS_ACTIVE_SHIFT 31
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#define CMDSTATUS_ACTIVE_MASK (1 << 31)
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#define CMDSTATUS_ERR_MASK 0xFF
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#ifdef __cplusplus
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}
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#endif
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#endif /* IOAT_HW_DEFS_H */
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