04e8ec7419
There were defines which originally allowed sharing of some code with the enic kernel driver. The code has long since diverged and now the abstraction just makes the code harder to read. Mostly mechanical replacement of defines and reformatting. Signed-off-by: John Daley <johndale@cisco.com> Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>
100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _CQ_DESC_H_
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#define _CQ_DESC_H_
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#include <rte_byteorder.h>
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/*
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* Completion queue descriptor types
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*/
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enum cq_desc_types {
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CQ_DESC_TYPE_WQ_ENET = 0,
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CQ_DESC_TYPE_DESC_COPY = 1,
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CQ_DESC_TYPE_WQ_EXCH = 2,
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CQ_DESC_TYPE_RQ_ENET = 3,
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CQ_DESC_TYPE_RQ_FCP = 4,
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CQ_DESC_TYPE_IOMMU_MISS = 5,
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CQ_DESC_TYPE_SGL = 6,
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CQ_DESC_TYPE_CLASSIFIER = 7,
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CQ_DESC_TYPE_TEST = 127,
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};
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/* Completion queue descriptor: 16B
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*
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* All completion queues have this basic layout. The
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* type_specific area is unique for each completion
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* queue type.
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*/
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struct cq_desc {
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uint16_t completed_index;
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uint16_t q_number;
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uint8_t type_specific[11];
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uint8_t type_color;
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};
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#define CQ_DESC_TYPE_BITS 4
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#define CQ_DESC_TYPE_MASK ((1 << CQ_DESC_TYPE_BITS) - 1)
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#define CQ_DESC_COLOR_MASK 1
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#define CQ_DESC_COLOR_SHIFT 7
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#define CQ_DESC_COLOR_MASK_NOSHIFT 0x80
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#define CQ_DESC_Q_NUM_BITS 10
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#define CQ_DESC_Q_NUM_MASK ((1 << CQ_DESC_Q_NUM_BITS) - 1)
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#define CQ_DESC_COMP_NDX_BITS 12
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#define CQ_DESC_COMP_NDX_MASK ((1 << CQ_DESC_COMP_NDX_BITS) - 1)
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static inline void cq_color_enc(struct cq_desc *desc, const uint8_t color)
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{
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if (color)
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desc->type_color |= (1 << CQ_DESC_COLOR_SHIFT);
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else
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desc->type_color &= ~(1 << CQ_DESC_COLOR_SHIFT);
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}
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static inline void cq_desc_enc(struct cq_desc *desc,
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const uint8_t type, const uint8_t color, const uint16_t q_number,
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const uint16_t completed_index)
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{
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desc->type_color = (type & CQ_DESC_TYPE_MASK) |
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((color & CQ_DESC_COLOR_MASK) << CQ_DESC_COLOR_SHIFT);
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desc->q_number = rte_cpu_to_le_16(q_number & CQ_DESC_Q_NUM_MASK);
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desc->completed_index = rte_cpu_to_le_16(completed_index &
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CQ_DESC_COMP_NDX_MASK);
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}
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static inline void cq_desc_dec(const struct cq_desc *desc_arg,
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uint8_t *type, uint8_t *color, uint16_t *q_number,
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uint16_t *completed_index)
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{
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const struct cq_desc *desc = desc_arg;
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const uint8_t type_color = desc->type_color;
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*color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
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/*
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* Make sure color bit is read from desc *before* other fields
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* are read from desc. Hardware guarantees color bit is last
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* bit (byte) written. Adding the rmb() prevents the compiler
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* and/or CPU from reordering the reads which would potentially
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* result in reading stale values.
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*/
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rte_rmb();
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*type = type_color & CQ_DESC_TYPE_MASK;
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*q_number = rte_le_to_cpu_16(desc->q_number) & CQ_DESC_Q_NUM_MASK;
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*completed_index = rte_le_to_cpu_16(desc->completed_index) &
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CQ_DESC_COMP_NDX_MASK;
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}
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static inline void cq_color_dec(const struct cq_desc *desc_arg, uint8_t *color)
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{
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volatile const struct cq_desc *desc = desc_arg;
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*color = (desc->type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
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}
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#endif /* _CQ_DESC_H_ */
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