2171c38eed
ipn3ke can work on 10G mode and 25G mode.
10G mode and 25G mode has different MAC register address for statistics.
This patch implements statistics registers for 10G mode and 25G mode.
Also implements different stats clearing per mode.
Fixes: c01c748e4a ("net/ipn3ke: add new driver")
Cc: stable@dpdk.org
Signed-off-by: Andy Pei <andy.pei@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
724 lines
18 KiB
C
724 lines
18 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#include <stdint.h>
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#include <rte_bus_pci.h>
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#include <rte_ethdev.h>
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#include <rte_pci.h>
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#include <rte_malloc.h>
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#include <rte_mbuf.h>
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#include <rte_sched.h>
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#include <rte_ethdev_driver.h>
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#include <rte_io.h>
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#include <rte_rawdev.h>
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#include <rte_rawdev_pmd.h>
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#include <rte_bus_ifpga.h>
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#include <ifpga_common.h>
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#include <ifpga_logs.h>
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#include "ipn3ke_rawdev_api.h"
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#include "ipn3ke_flow.h"
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#include "ipn3ke_logs.h"
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#include "ipn3ke_ethdev.h"
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int ipn3ke_afu_logtype;
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static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = {
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{ MAP_UUID_10G_LOW, MAP_UUID_10G_HIGH },
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{ IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH },
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{ IPN3KE_UUID_VBNG_LOW, IPN3KE_UUID_VBNG_HIGH},
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{ IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH },
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{ 0, 0 /* sentinel */ },
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};
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static int
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ipn3ke_indirect_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
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uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
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{
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uint32_t i, try_cnt;
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uint64_t indirect_value;
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volatile void *indirect_addrs;
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uint64_t target_addr;
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uint64_t read_data = 0;
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if (eth_group_sel != 0 && eth_group_sel != 1)
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return -1;
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target_addr = addr | dev_sel << 17;
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indirect_value = RCMD | target_addr << 32;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
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rte_delay_us(10);
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rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
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i = 0;
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try_cnt = 10;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] +
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0x18;
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do {
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read_data = rte_read64(indirect_addrs);
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if ((read_data >> 32) == 1)
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break;
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i++;
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} while (i <= try_cnt);
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if (i > try_cnt)
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return -1;
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*rd_data = rte_le_to_cpu_32(read_data);
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return 0;
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}
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static int
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ipn3ke_indirect_write(struct ipn3ke_hw *hw, uint32_t wr_data,
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uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
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{
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volatile void *indirect_addrs;
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uint64_t indirect_value;
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uint64_t target_addr;
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if (eth_group_sel != 0 && eth_group_sel != 1)
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return -1;
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target_addr = addr | dev_sel << 17;
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indirect_value = WCMD | target_addr << 32 | wr_data;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
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rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
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return 0;
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}
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static int
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ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
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uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
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{
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uint32_t dev_sel;
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if (mac_num >= hw->port_num)
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return -1;
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mac_num &= 0x7;
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dev_sel = mac_num * 2 + 3;
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return ipn3ke_indirect_read(hw, rd_data, addr, dev_sel, eth_group_sel);
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}
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static int
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ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw, uint32_t wr_data,
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uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
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{
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uint32_t dev_sel;
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if (mac_num >= hw->port_num)
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return -1;
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mac_num &= 0x7;
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dev_sel = mac_num * 2 + 3;
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return ipn3ke_indirect_write(hw, wr_data, addr, dev_sel, eth_group_sel);
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}
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static void
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ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)
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{
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hw->hw_cap.version_number = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0), 0, 0xFFFF);
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hw->hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF);
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hw->hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF);
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hw->hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF);
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hw->hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF);
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hw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x24), 0, 0xFFFF);
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hw->hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF);
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hw->hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF);
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hw->hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF);
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hw->hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x34), 0, 0xFFFF);
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hw->hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF);
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hw->hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF);
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hw->hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF);
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hw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x44), 0, 0xFFFF);
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hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF);
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hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF);
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hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF);
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hw->hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x54), 0, 0xFFFF);
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hw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF);
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hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF);
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hw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0, 0xFFFF);
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hw->hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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4, 0xFFFF);
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hw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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8, 0xFFFF);
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hw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0xC, 0xFFFF);
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hw->hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0x10, 0xFFFF);
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hw->hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET,
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0, 0xFFFFF);
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}
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static int
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ipn3ke_vbng_init_done(struct ipn3ke_hw *hw)
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{
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uint32_t timeout = 10000;
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while (timeout > 0) {
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if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS)
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== IPN3KE_VBNG_INIT_DONE)
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break;
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rte_delay_us(1000);
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timeout--;
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}
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if (!timeout) {
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IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n");
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return -1;
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}
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return 0;
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}
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static int
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ipn3ke_hw_init(struct rte_afu_device *afu_dev,
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struct ipn3ke_hw *hw)
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{
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struct rte_rawdev *rawdev;
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int ret;
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int i;
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uint64_t port_num, mac_type, index;
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rawdev = afu_dev->rawdev;
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hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;
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hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;
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hw->afu_id.port = afu_dev->id.port;
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hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);
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hw->f_mac_read = ipn3ke_indirect_mac_read;
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hw->f_mac_write = ipn3ke_indirect_mac_write;
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hw->rawdev = rawdev;
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideBARIndex", &index);
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hw->eth_group_bar[0] = (uint8_t *)(afu_dev->mem_resource[index].addr);
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rawdev->dev_ops->attr_get(rawdev,
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"NICSideBARIndex", &index);
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hw->eth_group_bar[1] = (uint8_t *)(afu_dev->mem_resource[index].addr);
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideLinkPortNum", &port_num);
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hw->retimer.port_num = (int)port_num;
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hw->port_num = hw->retimer.port_num;
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideMACType", &mac_type);
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hw->retimer.mac_type = (int)mac_type;
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IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
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if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
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afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
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/* After power on, wait until init done */
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if (ipn3ke_vbng_init_done(hw))
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return -1;
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ipn3ke_hw_cap_init(hw);
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/* Reset vBNG IP */
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IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
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rte_delay_us(10);
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IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
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/* After reset, wait until init done */
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if (ipn3ke_vbng_init_done(hw))
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return -1;
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}
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if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
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/* Enable inter connect channel */
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for (i = 0; i < hw->port_num; i++) {
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/* Enable the TX path */
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ipn3ke_xmac_tx_enable(hw, i, 1);
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/* Disables source address override */
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ipn3ke_xmac_smac_ovd_dis(hw, i, 1);
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/* Enable the RX path */
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ipn3ke_xmac_rx_enable(hw, i, 1);
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
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/* Clear line RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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/* Enable inter connect channel */
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for (i = 0; i < hw->port_num; i++) {
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
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}
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}
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ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
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if (ret)
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IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d",
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ret);
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hw->tm_hw_enable = 0;
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hw->flow_hw_enable = 0;
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if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
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afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
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ret = ipn3ke_hw_tm_init(hw);
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if (ret)
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return ret;
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hw->tm_hw_enable = 1;
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ret = ipn3ke_flow_init(hw);
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if (ret)
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return ret;
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hw->flow_hw_enable = 1;
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}
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hw->acc_tm = 0;
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hw->acc_flow = 0;
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return 0;
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}
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static void
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ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
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{
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int i;
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if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
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for (i = 0; i < hw->port_num; i++) {
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/* Disable the TX path */
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ipn3ke_xmac_tx_disable(hw, i, 1);
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/* Disable the RX path */
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ipn3ke_xmac_rx_disable(hw, i, 1);
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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for (i = 0; i < hw->port_num; i++) {
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
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}
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}
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}
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static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev)
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{
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char name[RTE_ETH_NAME_MAX_LEN];
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struct ipn3ke_hw *hw;
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int i, retval;
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/* check if the AFU device has been probed already */
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/* allocate shared mcp_vswitch structure */
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if (!afu_dev->shared.data) {
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snprintf(name, sizeof(name), "net_%s_hw",
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afu_dev->device.name);
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hw = rte_zmalloc_socket(name,
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sizeof(struct ipn3ke_hw),
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RTE_CACHE_LINE_SIZE,
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afu_dev->device.numa_node);
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if (!hw) {
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IPN3KE_AFU_PMD_ERR("failed to allocate hardwart data");
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retval = -ENOMEM;
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return -ENOMEM;
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}
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afu_dev->shared.data = hw;
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rte_spinlock_init(&afu_dev->shared.lock);
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} else {
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hw = afu_dev->shared.data;
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}
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retval = ipn3ke_hw_init(afu_dev, hw);
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if (retval)
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return retval;
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/* probe representor ports */
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for (i = 0; i < hw->port_num; i++) {
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struct ipn3ke_rpst rpst = {
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.port_id = i,
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.switch_domain_id = hw->switch_domain_id,
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.hw = hw
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};
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/* representor port net_bdf_port */
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snprintf(name, sizeof(name), "net_%s_representor_%d",
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afu_dev->device.name, i);
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retval = rte_eth_dev_create(&afu_dev->device, name,
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sizeof(struct ipn3ke_rpst), NULL, NULL,
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ipn3ke_rpst_init, &rpst);
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if (retval)
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IPN3KE_AFU_PMD_ERR("failed to create ipn3ke representor %s.",
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name);
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}
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return 0;
|
|
}
|
|
|
|
static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev)
|
|
{
|
|
char name[RTE_ETH_NAME_MAX_LEN];
|
|
struct ipn3ke_hw *hw;
|
|
struct rte_eth_dev *ethdev;
|
|
int i, ret;
|
|
|
|
hw = afu_dev->shared.data;
|
|
|
|
/* remove representor ports */
|
|
for (i = 0; i < hw->port_num; i++) {
|
|
/* representor port net_bdf_port */
|
|
snprintf(name, sizeof(name), "net_%s_representor_%d",
|
|
afu_dev->device.name, i);
|
|
|
|
ethdev = rte_eth_dev_allocated(afu_dev->device.name);
|
|
if (!ethdev)
|
|
return -ENODEV;
|
|
|
|
rte_eth_dev_destroy(ethdev, ipn3ke_rpst_uninit);
|
|
}
|
|
|
|
ret = rte_eth_switch_domain_free(hw->switch_domain_id);
|
|
if (ret)
|
|
IPN3KE_AFU_PMD_WARN("failed to free switch domain: %d", ret);
|
|
|
|
/* hw uninit*/
|
|
ipn3ke_hw_uninit(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct rte_afu_driver afu_ipn3ke_driver = {
|
|
.id_table = afu_uuid_ipn3ke_map,
|
|
.probe = ipn3ke_vswitch_probe,
|
|
.remove = ipn3ke_vswitch_remove,
|
|
};
|
|
|
|
RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);
|
|
|
|
static const char * const valid_args[] = {
|
|
#define IPN3KE_AFU_NAME "afu"
|
|
IPN3KE_AFU_NAME,
|
|
#define IPN3KE_FPGA_ACCELERATION_LIST "fpga_acc"
|
|
IPN3KE_FPGA_ACCELERATION_LIST,
|
|
#define IPN3KE_I40E_PF_LIST "i40e_pf"
|
|
IPN3KE_I40E_PF_LIST,
|
|
NULL
|
|
};
|
|
|
|
static int
|
|
ipn3ke_cfg_parse_acc_list(const char *afu_name,
|
|
const char *acc_list_name)
|
|
{
|
|
struct rte_afu_device *afu_dev;
|
|
struct ipn3ke_hw *hw;
|
|
const char *p_source;
|
|
char *p_start;
|
|
char name[RTE_ETH_NAME_MAX_LEN];
|
|
|
|
afu_dev = rte_ifpga_find_afu_by_name(afu_name);
|
|
if (!afu_dev)
|
|
return -1;
|
|
hw = afu_dev->shared.data;
|
|
if (!hw)
|
|
return -1;
|
|
|
|
p_source = acc_list_name;
|
|
while (*p_source) {
|
|
while ((*p_source == '{') || (*p_source == '|'))
|
|
p_source++;
|
|
p_start = name;
|
|
while ((*p_source != '|') && (*p_source != '}'))
|
|
*p_start++ = *p_source++;
|
|
*p_start = 0;
|
|
if (!strcmp(name, "tm") && hw->tm_hw_enable)
|
|
hw->acc_tm = 1;
|
|
|
|
if (!strcmp(name, "flow") && hw->flow_hw_enable)
|
|
hw->acc_flow = 1;
|
|
|
|
if (*p_source == '}')
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ipn3ke_cfg_parse_i40e_pf_ethdev(const char *afu_name,
|
|
const char *pf_name)
|
|
{
|
|
struct rte_eth_dev *i40e_eth, *rpst_eth;
|
|
struct rte_afu_device *afu_dev;
|
|
struct ipn3ke_rpst *rpst;
|
|
struct ipn3ke_hw *hw;
|
|
const char *p_source;
|
|
char *p_start;
|
|
char name[RTE_ETH_NAME_MAX_LEN];
|
|
uint16_t port_id;
|
|
int i;
|
|
int ret = -1;
|
|
|
|
afu_dev = rte_ifpga_find_afu_by_name(afu_name);
|
|
if (!afu_dev)
|
|
return -1;
|
|
hw = afu_dev->shared.data;
|
|
if (!hw)
|
|
return -1;
|
|
|
|
p_source = pf_name;
|
|
for (i = 0; i < hw->port_num; i++) {
|
|
snprintf(name, sizeof(name), "net_%s_representor_%d",
|
|
afu_name, i);
|
|
ret = rte_eth_dev_get_port_by_name(name, &port_id);
|
|
if (ret)
|
|
return -1;
|
|
rpst_eth = &rte_eth_devices[port_id];
|
|
rpst = IPN3KE_DEV_PRIVATE_TO_RPST(rpst_eth);
|
|
|
|
while ((*p_source == '{') || (*p_source == '|'))
|
|
p_source++;
|
|
p_start = name;
|
|
while ((*p_source != '|') && (*p_source != '}'))
|
|
*p_start++ = *p_source++;
|
|
*p_start = 0;
|
|
|
|
ret = rte_eth_dev_get_port_by_name(name, &port_id);
|
|
if (ret)
|
|
return -1;
|
|
i40e_eth = &rte_eth_devices[port_id];
|
|
|
|
rpst->i40e_pf_eth = i40e_eth;
|
|
rpst->i40e_pf_eth_port_id = port_id;
|
|
|
|
if ((*p_source == '}') || !(*p_source))
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ipn3ke_cfg_probe(struct rte_vdev_device *dev)
|
|
{
|
|
struct rte_devargs *devargs;
|
|
struct rte_kvargs *kvlist = NULL;
|
|
char *afu_name = NULL;
|
|
char *acc_name = NULL;
|
|
char *pf_name = NULL;
|
|
int afu_name_en = 0;
|
|
int acc_list_en = 0;
|
|
int pf_list_en = 0;
|
|
int ret = -1;
|
|
|
|
devargs = dev->device.devargs;
|
|
|
|
kvlist = rte_kvargs_parse(devargs->args, valid_args);
|
|
if (!kvlist) {
|
|
IPN3KE_AFU_PMD_ERR("error when parsing param");
|
|
goto end;
|
|
}
|
|
|
|
if (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {
|
|
if (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,
|
|
&rte_ifpga_get_string_arg,
|
|
&afu_name) < 0) {
|
|
IPN3KE_AFU_PMD_ERR("error to parse %s",
|
|
IPN3KE_AFU_NAME);
|
|
goto end;
|
|
} else {
|
|
afu_name_en = 1;
|
|
}
|
|
}
|
|
|
|
if (rte_kvargs_count(kvlist, IPN3KE_FPGA_ACCELERATION_LIST) == 1) {
|
|
if (rte_kvargs_process(kvlist, IPN3KE_FPGA_ACCELERATION_LIST,
|
|
&rte_ifpga_get_string_arg,
|
|
&acc_name) < 0) {
|
|
IPN3KE_AFU_PMD_ERR("error to parse %s",
|
|
IPN3KE_FPGA_ACCELERATION_LIST);
|
|
goto end;
|
|
} else {
|
|
acc_list_en = 1;
|
|
}
|
|
}
|
|
|
|
if (rte_kvargs_count(kvlist, IPN3KE_I40E_PF_LIST) == 1) {
|
|
if (rte_kvargs_process(kvlist, IPN3KE_I40E_PF_LIST,
|
|
&rte_ifpga_get_string_arg,
|
|
&pf_name) < 0) {
|
|
IPN3KE_AFU_PMD_ERR("error to parse %s",
|
|
IPN3KE_I40E_PF_LIST);
|
|
goto end;
|
|
} else {
|
|
pf_list_en = 1;
|
|
}
|
|
}
|
|
|
|
if (!afu_name_en) {
|
|
IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
|
|
IPN3KE_AFU_NAME);
|
|
goto end;
|
|
}
|
|
|
|
if (!pf_list_en) {
|
|
IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
|
|
IPN3KE_I40E_PF_LIST);
|
|
goto end;
|
|
}
|
|
|
|
if (acc_list_en) {
|
|
ret = ipn3ke_cfg_parse_acc_list(afu_name, acc_name);
|
|
if (ret) {
|
|
IPN3KE_AFU_PMD_ERR("arg %s parse error for ipn3ke",
|
|
IPN3KE_FPGA_ACCELERATION_LIST);
|
|
goto end;
|
|
}
|
|
} else {
|
|
IPN3KE_AFU_PMD_INFO("arg %s is optional for ipn3ke, using i40e acc",
|
|
IPN3KE_FPGA_ACCELERATION_LIST);
|
|
}
|
|
|
|
ret = ipn3ke_cfg_parse_i40e_pf_ethdev(afu_name, pf_name);
|
|
if (ret)
|
|
goto end;
|
|
end:
|
|
if (kvlist)
|
|
rte_kvargs_free(kvlist);
|
|
if (afu_name)
|
|
free(afu_name);
|
|
if (acc_name)
|
|
free(acc_name);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
ipn3ke_cfg_remove(struct rte_vdev_device *dev)
|
|
{
|
|
struct rte_devargs *devargs;
|
|
struct rte_kvargs *kvlist = NULL;
|
|
char *afu_name = NULL;
|
|
struct rte_afu_device *afu_dev;
|
|
int ret = -1;
|
|
|
|
devargs = dev->device.devargs;
|
|
|
|
kvlist = rte_kvargs_parse(devargs->args, valid_args);
|
|
if (!kvlist) {
|
|
IPN3KE_AFU_PMD_ERR("error when parsing param");
|
|
goto end;
|
|
}
|
|
|
|
if (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {
|
|
if (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,
|
|
&rte_ifpga_get_string_arg,
|
|
&afu_name) < 0) {
|
|
IPN3KE_AFU_PMD_ERR("error to parse %s",
|
|
IPN3KE_AFU_NAME);
|
|
} else {
|
|
afu_dev = rte_ifpga_find_afu_by_name(afu_name);
|
|
if (!afu_dev)
|
|
goto end;
|
|
ret = ipn3ke_vswitch_remove(afu_dev);
|
|
}
|
|
} else {
|
|
IPN3KE_AFU_PMD_ERR("Remove ipn3ke_cfg %p error", dev);
|
|
}
|
|
|
|
end:
|
|
if (kvlist)
|
|
rte_kvargs_free(kvlist);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct rte_vdev_driver ipn3ke_cfg_driver = {
|
|
.probe = ipn3ke_cfg_probe,
|
|
.remove = ipn3ke_cfg_remove,
|
|
};
|
|
|
|
RTE_PMD_REGISTER_VDEV(ipn3ke_cfg, ipn3ke_cfg_driver);
|
|
RTE_PMD_REGISTER_PARAM_STRING(ipn3ke_cfg,
|
|
"afu=<string> "
|
|
"fpga_acc=<string>"
|
|
"i40e_pf=<string>");
|
|
|
|
RTE_INIT(ipn3ke_afu_init_log)
|
|
{
|
|
ipn3ke_afu_logtype = rte_log_register("pmd.afu.ipn3ke");
|
|
if (ipn3ke_afu_logtype >= 0)
|
|
rte_log_set_level(ipn3ke_afu_logtype, RTE_LOG_NOTICE);
|
|
}
|