e622c1a88e
Need to set configure flag to allow create and commit mrvl tm
hierarchy tree. tm configuration depends on parameters that are
being set in port configure stage, e.g. nb_tx_queues.
This also aligned with the tm api description.
Fixes: 429c394417
("net/mvpp2: support traffic manager")
Cc: stable@dpdk.org
Signed-off-by: Dana Vardi <danat@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
253 lines
6.1 KiB
C
253 lines
6.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Marvell International Ltd.
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* Copyright(c) 2017 Semihalf.
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* All rights reserved.
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*/
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#ifndef _MRVL_ETHDEV_H_
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#define _MRVL_ETHDEV_H_
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#include <rte_spinlock.h>
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#include <rte_flow_driver.h>
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#include <rte_mtr_driver.h>
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#include <rte_tm_driver.h>
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/*
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* container_of is defined by both DPDK and MUSDK,
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* we'll declare only one version.
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*
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* Note that it is not used in this PMD anyway.
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*/
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#ifdef container_of
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#undef container_of
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#endif
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#include <env/mv_autogen_comp_flags.h>
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#include <drivers/mv_pp2.h>
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#include <drivers/mv_pp2_bpool.h>
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#include <drivers/mv_pp2_cls.h>
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#include <drivers/mv_pp2_hif.h>
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#include <drivers/mv_pp2_ppio.h>
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#include "env/mv_common.h" /* for BIT() */
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/** Maximum number of rx queues per port */
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#define MRVL_PP2_RXQ_MAX 32
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/** Maximum number of tx queues per port */
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#define MRVL_PP2_TXQ_MAX 8
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/** Minimum number of descriptors in tx queue */
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#define MRVL_PP2_TXD_MIN 16
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/** Maximum number of descriptors in tx queue */
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#define MRVL_PP2_TXD_MAX 2048
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/** Tx queue descriptors alignment */
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#define MRVL_PP2_TXD_ALIGN 16
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/** Minimum number of descriptors in rx queue */
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#define MRVL_PP2_RXD_MIN 16
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/** Maximum number of descriptors in rx queue */
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#define MRVL_PP2_RXD_MAX 2048
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/** Rx queue descriptors alignment */
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#define MRVL_PP2_RXD_ALIGN 16
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/** Maximum number of descriptors in tx aggregated queue */
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#define MRVL_PP2_AGGR_TXQD_MAX 2048
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/** Maximum number of Traffic Classes. */
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#define MRVL_PP2_TC_MAX 8
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/** Packet offset inside RX buffer. */
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#define MRVL_PKT_OFFS 64
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/** Maximum number of descriptors in shadow queue. Must be power of 2 */
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#define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
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/** Shadow queue size mask (since shadow queue size is power of 2) */
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#define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
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/** Minimum number of sent buffers to release from shadow queue to BM */
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#define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
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#define MRVL_PP2_VLAN_TAG_LEN 4
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#define MRVL_PP2_ETH_HDRS_LEN (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
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(2 * MRVL_PP2_VLAN_TAG_LEN))
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#define MRVL_PP2_HDRS_LEN (MV_MH_SIZE + MRVL_PP2_ETH_HDRS_LEN)
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#define MRVL_PP2_MTU_TO_MRU(mtu) ((mtu) + MRVL_PP2_HDRS_LEN)
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#define MRVL_PP2_MRU_TO_MTU(mru) ((mru) - MRVL_PP2_HDRS_LEN)
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/** Maximum length of a match string */
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#define MRVL_MATCH_LEN 16
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#define MRVL_BURST_SIZE 64
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/** PMD-specific definition of a flow rule handle. */
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struct mrvl_mtr;
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struct rte_flow {
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LIST_ENTRY(rte_flow) next;
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struct mrvl_mtr *mtr;
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struct pp2_cls_tbl_key table_key;
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struct pp2_cls_tbl_rule rule;
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struct pp2_cls_cos_desc cos;
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struct pp2_cls_tbl_action action;
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uint8_t next_udf_id;
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};
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struct mrvl_mtr_profile {
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LIST_ENTRY(mrvl_mtr_profile) next;
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uint32_t profile_id;
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int refcnt;
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struct rte_mtr_meter_profile profile;
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};
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struct mrvl_mtr {
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LIST_ENTRY(mrvl_mtr) next;
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uint32_t mtr_id;
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int refcnt;
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int shared;
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int enabled;
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int plcr_bit;
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struct mrvl_mtr_profile *profile;
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struct pp2_cls_plcr *plcr;
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};
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struct mrvl_tm_shaper_profile {
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LIST_ENTRY(mrvl_tm_shaper_profile) next;
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uint32_t id;
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int refcnt;
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struct rte_tm_shaper_params params;
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};
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enum {
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MRVL_NODE_PORT,
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MRVL_NODE_QUEUE,
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};
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struct mrvl_tm_node {
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LIST_ENTRY(mrvl_tm_node) next;
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uint32_t id;
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uint32_t type;
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int refcnt;
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struct mrvl_tm_node *parent;
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struct mrvl_tm_shaper_profile *profile;
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uint8_t weight;
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uint64_t stats_mask;
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};
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struct mrvl_priv {
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/* Hot fields, used in fast path. */
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struct pp2_bpool *bpool; /**< BPool pointer */
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struct pp2_ppio *ppio; /**< Port handler pointer */
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rte_spinlock_t lock; /**< Spinlock for checking bpool status */
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uint16_t bpool_max_size; /**< BPool maximum size */
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uint16_t bpool_min_size; /**< BPool minimum size */
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uint16_t bpool_init_size; /**< Configured BPool size */
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/** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
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struct {
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uint8_t tc; /**< Traffic Class */
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uint8_t inq; /**< Relative in-queue number */
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} rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
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/* Configuration data, used sporadically. */
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uint8_t pp_id;
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uint8_t ppio_id;
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uint8_t bpool_bit;
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uint8_t rss_hf_tcp;
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uint8_t uc_mc_flushed;
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uint8_t isolated;
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uint8_t multiseg;
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uint16_t max_mtu;
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uint8_t flow_ctrl;
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struct rte_eth_fc_conf fc_conf;
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struct pp2_ppio_params ppio_params;
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struct pp2_cls_qos_tbl_params qos_tbl_params;
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struct pp2_cls_tbl *qos_tbl;
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uint16_t nb_rx_queues;
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struct pp2_cls_tbl_params cls_tbl_params;
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struct pp2_cls_tbl *cls_tbl;
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LIST_HEAD(mrvl_flows, rte_flow) flows;
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struct pp2_cls_plcr *default_policer;
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LIST_HEAD(profiles, mrvl_mtr_profile) profiles;
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LIST_HEAD(mtrs, mrvl_mtr) mtrs;
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uint32_t used_plcrs;
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LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles;
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LIST_HEAD(nodes, mrvl_tm_node) nodes;
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uint64_t rate_max;
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uint8_t forward_bad_frames;
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uint32_t fill_bpool_buffs;
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uint8_t configured; /** indicates if device has been configured */
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};
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/** Flow operations forward declaration. */
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extern const struct rte_flow_ops mrvl_flow_ops;
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/** Meter operations forward declaration. */
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extern const struct rte_mtr_ops mrvl_mtr_ops;
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/** Traffic manager operations forward declaration. */
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extern const struct rte_tm_ops mrvl_tm_ops;
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/** Current log type. */
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extern int mrvl_logtype;
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#define MRVL_LOG(level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
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__func__, ##args)
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extern struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC];
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/**
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* Convert string to uint32_t with extra checks for result correctness.
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*
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* @param string String to convert.
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* @param val Conversion result.
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* @returns 0 in case of success, negative value otherwise.
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*/
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static int
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get_val_securely(const char *string, uint32_t *val)
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{
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char *endptr;
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size_t len = strlen(string);
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if (len == 0)
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return -1;
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errno = 0;
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*val = strtoul(string, &endptr, 0);
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if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len)
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return -2;
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return 0;
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}
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static int
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get_val_securely8(const char *string, uint32_t base, uint8_t *val)
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{
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char *endptr;
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size_t len = strlen(string);
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if (len == 0)
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return -1;
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errno = 0;
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*val = (uint8_t)strtoul(string, &endptr, base);
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if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len)
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return -2;
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return 0;
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}
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#endif /* _MRVL_ETHDEV_H_ */
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