f22e705ebf
Add all necessary elements for DPDK to compile and run EAL on SiFive Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc) core complex. This includes: - EAL library implementation for rv64imafdc ISA. - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the U74 core. Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain. Clang compilation currently not supported due to issues with missing relocation relaxation. Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime (default) and unstable high-resolution using rdcycle. User can override the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of both DPDK and the application. The reasoning for this is as follows. The RISC-V ISA mandates that clock read by rdtime has to be of constant period and synchronized between all hardware threads within 1 tick (chapter 10.1 in version 20191213 of RISC-V spec). However this clock may not be of high-enough frequency for dataplane uses. I.e. on HiFive Unmatched (FU740) it is 1MHz. There is a high-resolution alternative in form of rdcycle which is clocked at the core clock frequency. The drawbacks are that it may be disabled during sleep (WFI), its frequency might change due to DVFS and it is core-local and therefore cannot be used as a wall-clock. It can however be used for micro-benchmarking user applications, similarly to Aarch64's PMCCNTR PMU counter. The platform is currently marked as linux-only because rte_cycles implementation uses the timebase-frequency device-tree node read through the proc file system. Such approach was chosen because Linux kernel depends on the presence of this device-tree node. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. The compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Sponsored-by: Frank Zhao <frank.zhao@starfivetech.com> Sponsored-by: Sam Grove <sam.grove@sifive.com> Signed-off-by: Michal Mazurek <maz@semihalf.com> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015 Cavium, Inc
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* Copyright(c) 2022 StarFive
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* Copyright(c) 2022 SiFive
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* Copyright(c) 2022 Semihalf
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*/
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#include <stdio.h>
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#include "eal_private.h"
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#include "rte_byteorder.h"
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#include "rte_cycles.h"
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#include "rte_log.h"
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/** Read generic counter frequency */
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static uint64_t
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__rte_riscv_timefrq(void)
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{
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#define TIMEBASE_FREQ_SIZE 8
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if (RTE_RISCV_TIME_FREQ > 0)
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return RTE_RISCV_TIME_FREQ;
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uint8_t buf[TIMEBASE_FREQ_SIZE];
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ssize_t cnt;
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FILE *file;
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file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb");
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if (!file)
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goto fail;
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cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);
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fclose(file);
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switch (cnt) {
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case 8:
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return rte_be_to_cpu_64(*(uint64_t *)buf);
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case 4:
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return rte_be_to_cpu_32(*(uint32_t *)buf);
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default:
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break;
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}
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fail:
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RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n");
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return 0;
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}
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uint64_t
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get_tsc_freq_arch(void)
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{
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RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n",
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RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime");
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if (!RTE_RISCV_RDTSC_USE_HPM)
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return __rte_riscv_timefrq();
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#define CYC_PER_1MHZ 1E6
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/*
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* Use real time clock to estimate current cycle frequency
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*/
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uint64_t ticks, frq;
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uint64_t start_ticks, cur_ticks;
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uint64_t start_cycle, end_cycle;
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/* Do not proceed unless clock frequency can be obtained. */
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frq = __rte_riscv_timefrq();
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if (!frq)
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return 0;
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/* Number of ticks for 1/10 second */
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ticks = frq / 10;
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start_ticks = __rte_riscv_rdtime_precise();
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start_cycle = rte_rdtsc_precise();
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do {
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cur_ticks = __rte_riscv_rdtime();
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} while ((cur_ticks - start_ticks) < ticks);
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end_cycle = rte_rdtsc_precise();
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/* Adjust the cycles to next 1Mhz */
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return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);
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}
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