df96fd0d73
The rte_ethdev_driver.h, rte_ethdev_vdev.h and rte_ethdev_pci.h files are for drivers only and should be a private to DPDK and not installed. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Steven Webster <steven.webster@windriver.com>
117 lines
2.4 KiB
C
117 lines
2.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2016 Cavium, Inc
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*/
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#ifndef _THUNDERX_NICVF_STRUCT_H
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#define _THUNDERX_NICVF_STRUCT_H
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#include <stdint.h>
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#include <rte_spinlock.h>
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#include <rte_mempool.h>
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#include <rte_mbuf.h>
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#include <rte_interrupts.h>
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#include <ethdev_driver.h>
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#include <rte_memory.h>
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struct nicvf_rbdr {
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uintptr_t rbdr_status;
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uintptr_t rbdr_door;
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struct rbdr_entry_t *desc;
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nicvf_iova_addr_t phys;
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uint32_t buffsz;
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uint32_t tail;
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uint32_t next_tail;
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uint32_t head;
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uint32_t qlen_mask;
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} __rte_cache_aligned;
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struct nicvf_txq {
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union sq_entry_t *desc;
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nicvf_iova_addr_t phys;
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struct rte_mbuf **txbuffs;
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uintptr_t sq_head;
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uintptr_t sq_door;
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struct rte_mempool *pool;
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struct nicvf *nic;
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void (*pool_free)(struct nicvf_txq *sq);
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uint32_t head;
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uint32_t tail;
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int32_t xmit_bufs;
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uint32_t qlen_mask;
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uint64_t offloads;
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uint16_t queue_id;
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uint16_t tx_free_thresh;
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} __rte_cache_aligned;
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union mbuf_initializer {
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struct {
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uint16_t data_off;
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uint16_t refcnt;
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uint16_t nb_segs;
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uint16_t port;
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} fields;
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uint64_t value;
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};
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struct nicvf_rxq {
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RTE_MARKER rxq_fastpath_data_start;
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uint8_t rbptr_offset;
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uint16_t rx_free_thresh;
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uint32_t head;
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uint32_t qlen_mask;
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int32_t recv_buffers;
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int32_t available_space;
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uint64_t mbuf_phys_off;
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uintptr_t cq_status;
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uintptr_t cq_door;
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struct nicvf_rbdr *shared_rbdr;
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struct rte_mempool *pool;
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union cq_entry_t *desc;
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union mbuf_initializer mbuf_initializer;
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RTE_MARKER rxq_fastpath_data_end;
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uint8_t rx_drop_en;
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uint16_t precharge_cnt;
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uint16_t port_id;
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uint16_t queue_id;
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struct nicvf *nic;
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nicvf_iova_addr_t phys;
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} __rte_cache_aligned;
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struct nicvf {
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uint8_t vf_id;
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uint8_t node;
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uintptr_t reg_base;
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bool tns_mode;
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bool sqs_mode;
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bool loopback_supported;
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bool pf_acked:1;
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bool pf_nacked:1;
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bool offload_cksum:1;
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bool vlan_strip:1;
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uint64_t hwcap;
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uint8_t link_up;
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uint8_t duplex;
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uint32_t speed;
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uint32_t msg_enable;
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uint16_t device_id;
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uint16_t vendor_id;
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uint16_t subsystem_device_id;
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uint16_t subsystem_vendor_id;
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struct nicvf_rbdr *rbdr;
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struct nicvf_rss_reta_info rss_info;
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struct rte_intr_handle intr_handle;
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uint8_t cpi_alg;
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uint16_t mtu;
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int skip_bytes;
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bool vlan_filter_en;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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/* secondary queue set support */
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uint8_t sqs_id;
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uint8_t sqs_count;
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#define MAX_SQS_PER_VF 11
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struct nicvf *snicvf[MAX_SQS_PER_VF];
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} __rte_cache_aligned;
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#endif /* _THUNDERX_NICVF_STRUCT_H */
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