fd61c749db
NICs uses different delays up to a second during their configuration. It makes no sense to busy-wait so long wasting CPU cycles and preventing any other threads to execute on the same CPU core. These busy polling are the rudiments that came from the kernel drivers where you can not sleep in interrupt context, but as we're in userspace, we're able and should sleep to allow other threads to run. Delays never called on rx/tx path, so this should not affect performance. Signed-off-by: Ilya Maximets <i.maximets@samsung.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
216 lines
5.9 KiB
C
216 lines
5.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2018
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*/
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#ifndef _I40E_OSDEP_H_
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#define _I40E_OSDEP_H_
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <rte_common.h>
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#include <rte_memcpy.h>
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#include <rte_byteorder.h>
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#include <rte_cycles.h>
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#include <rte_spinlock.h>
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#include <rte_log.h>
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#include <rte_io.h>
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#include "../i40e_logs.h"
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#define INLINE inline
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#define STATIC static
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typedef uint8_t u8;
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typedef int8_t s8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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typedef int32_t s32;
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typedef uint64_t u64;
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typedef enum i40e_status_code i40e_status;
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#define __iomem
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#define hw_dbg(hw, S, A...) do {} while (0)
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#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
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#define lower_32_bits(n) ((u32)(n))
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#define low_16_bits(x) ((x) & 0xFFFF)
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#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
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#ifndef ETH_ADDR_LEN
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#define ETH_ADDR_LEN 6
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#endif
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#ifndef __le16
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#define __le16 uint16_t
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#endif
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#ifndef __le32
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#define __le32 uint32_t
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#endif
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#ifndef __le64
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#define __le64 uint64_t
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#endif
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#ifndef __be16
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#define __be16 uint16_t
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#endif
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#ifndef __be32
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#define __be32 uint32_t
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#endif
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#ifndef __be64
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#define __be64 uint64_t
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#endif
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#define FALSE 0
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#define TRUE 1
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#define false 0
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#define true 1
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#define min(a,b) RTE_MIN(a,b)
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#define max(a,b) RTE_MAX(a,b)
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#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
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#define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)
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#define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)
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#define DEBUGFUNC(F) DEBUGOUT(F "\n")
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#define DEBUGOUT2 DEBUGOUT1
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#define DEBUGOUT3 DEBUGOUT2
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#define DEBUGOUT6 DEBUGOUT3
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#define DEBUGOUT7 DEBUGOUT6
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#define i40e_debug(h, m, s, ...) \
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do { \
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if (((m) & (h)->debug_mask)) \
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PMD_DRV_LOG_RAW(DEBUG, "i40e %02x.%x " s, \
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(h)->bus.device, (h)->bus.func, \
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##__VA_ARGS__); \
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} while (0)
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/* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
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* are required for reading/writing below registers, as reading/writing it
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* directly may not function correctly if the device is under heavy small
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* packet traffic. Note that those interfaces are available from FVL5 and not
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* suitable before the AdminQ is ready during initialization.
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*
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* I40E_PFQF_CTL_0
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* I40E_PFQF_HENA
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* I40E_PFQF_FDALLOC
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* I40E_PFQF_HREGION
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* I40E_PFLAN_QALLOC
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* I40E_VPQF_CTL
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* I40E_VFQF_HENA
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* I40E_VFQF_HREGION
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* I40E_VSIQF_CTL
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* I40E_VSILAN_QBASE
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* I40E_VSILAN_QTABLE
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* I40E_VSIQF_TCREGION
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* I40E_PFQF_HKEY
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* I40E_VFQF_HKEY
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* I40E_PRTQF_CTL_0
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* I40E_GLFCOE_RCTL
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* I40E_GLFCOE_RSOF
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* I40E_GLQF_CTL
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* I40E_GLQF_SWAP
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* I40E_GLQF_HASH_MSK
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* I40E_GLQF_HASH_INSET
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* I40E_GLQF_HSYM
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* I40E_GLQF_FC_MSK
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* I40E_GLQF_FC_INSET
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* I40E_GLQF_FD_MSK
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* I40E_PRTQF_FD_INSET
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* I40E_PRTQF_FD_FLXINSET
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* I40E_PRTQF_FD_MSK
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*/
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#define I40E_PCI_REG(reg) rte_read32(reg)
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#define I40E_PCI_REG_ADDR(a, reg) \
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((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
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static inline uint32_t i40e_read_addr(volatile void *addr)
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{
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return rte_le_to_cpu_32(I40E_PCI_REG(addr));
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}
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#define I40E_PCI_REG_WRITE(reg, value) \
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rte_write32((rte_cpu_to_le_32(value)), reg)
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#define I40E_PCI_REG_WRITE_RELAXED(reg, value) \
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rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
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#define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
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#define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
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#define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
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#define I40E_WRITE_REG(hw, reg, value) \
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I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
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#define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
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#define wr32(a, reg, value) \
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I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
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#define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))
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#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
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/* memory allocation tracking */
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struct i40e_dma_mem {
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void *va;
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u64 pa;
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u32 size;
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const void *zone;
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} __attribute__((packed));
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#define i40e_allocate_dma_mem(h, m, unused, s, a) \
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i40e_allocate_dma_mem_d(h, m, s, a)
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#define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)
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struct i40e_virt_mem {
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void *va;
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u32 size;
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} __attribute__((packed));
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#define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)
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#define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)
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#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
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#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
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#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
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#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
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#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
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#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
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#define cpu_to_le16(o) rte_cpu_to_le_16(o)
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#define cpu_to_le32(s) rte_cpu_to_le_32(s)
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#define cpu_to_le64(h) rte_cpu_to_le_64(h)
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#define le16_to_cpu(a) rte_le_to_cpu_16(a)
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#define le32_to_cpu(c) rte_le_to_cpu_32(c)
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#define le64_to_cpu(k) rte_le_to_cpu_64(k)
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/* SW spinlock */
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struct i40e_spinlock {
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rte_spinlock_t spinlock;
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};
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#define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)
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#define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)
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#define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)
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#define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)
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#define I40E_NTOHS(a) rte_be_to_cpu_16(a)
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#define I40E_NTOHL(a) rte_be_to_cpu_32(a)
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#define I40E_HTONS(a) rte_cpu_to_be_16(a)
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#define I40E_HTONL(a) rte_cpu_to_be_32(a)
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#define i40e_memset(a, b, c, d) memset((a), (b), (c))
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#define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
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#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
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#define DELAY(x) rte_delay_us_sleep(x)
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#define i40e_usec_delay(x) DELAY(x)
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#define i40e_msec_delay(x) DELAY(1000 * (x))
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#define udelay(x) DELAY(x)
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#define msleep(x) DELAY(1000*(x))
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#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
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#endif /* _I40E_OSDEP_H_ */
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