f35e5b3e07
There is a common macro __rte_aligned for alignment, which is now used where appropriate for consistency. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
262 lines
8.0 KiB
C
262 lines
8.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015 Cavium, Inc
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*/
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#include "acl_run.h"
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#include "acl_vect.h"
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struct _neon_acl_const {
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rte_xmm_t xmm_shuffle_input;
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rte_xmm_t xmm_index_mask;
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rte_xmm_t range_base;
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} neon_acl_const __rte_cache_aligned = {
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{
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.u32 = {0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c}
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},
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{
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.u32 = {RTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX,
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RTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX}
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},
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{
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.u32 = {0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c}
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},
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};
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/*
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* Resolve priority for multiple results (neon version).
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* This consists comparing the priority of the current traversal with the
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* running set of results for the packet.
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* For each result, keep a running array of the result (rule number) and
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* its priority for each category.
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*/
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static inline void
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resolve_priority_neon(uint64_t transition, int n, const struct rte_acl_ctx *ctx,
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struct parms *parms,
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const struct rte_acl_match_results *p,
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uint32_t categories)
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{
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uint32_t x;
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int32x4_t results, priority, results1, priority1;
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uint32x4_t selector;
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int32_t *saved_results, *saved_priority;
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for (x = 0; x < categories; x += RTE_ACL_RESULTS_MULTIPLIER) {
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saved_results = (int32_t *)(&parms[n].cmplt->results[x]);
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saved_priority = (int32_t *)(&parms[n].cmplt->priority[x]);
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/* get results and priorities for completed trie */
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results = vld1q_s32(
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(const int32_t *)&p[transition].results[x]);
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priority = vld1q_s32(
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(const int32_t *)&p[transition].priority[x]);
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/* if this is not the first completed trie */
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if (parms[n].cmplt->count != ctx->num_tries) {
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/* get running best results and their priorities */
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results1 = vld1q_s32(saved_results);
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priority1 = vld1q_s32(saved_priority);
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/* select results that are highest priority */
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selector = vcgtq_s32(priority1, priority);
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results = vbslq_s32(selector, results1, results);
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priority = vbslq_s32(selector, priority1, priority);
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}
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/* save running best results and their priorities */
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vst1q_s32(saved_results, results);
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vst1q_s32(saved_priority, priority);
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}
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}
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/*
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* Check for any match in 4 transitions
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*/
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static __rte_always_inline uint32_t
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check_any_match_x4(uint64_t val[])
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{
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return (val[0] | val[1] | val[2] | val[3]) & RTE_ACL_NODE_MATCH;
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}
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static __rte_always_inline void
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acl_match_check_x4(int slot, const struct rte_acl_ctx *ctx, struct parms *parms,
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struct acl_flow_data *flows, uint64_t transitions[])
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{
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while (check_any_match_x4(transitions)) {
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transitions[0] = acl_match_check(transitions[0], slot, ctx,
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parms, flows, resolve_priority_neon);
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transitions[1] = acl_match_check(transitions[1], slot + 1, ctx,
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parms, flows, resolve_priority_neon);
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transitions[2] = acl_match_check(transitions[2], slot + 2, ctx,
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parms, flows, resolve_priority_neon);
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transitions[3] = acl_match_check(transitions[3], slot + 3, ctx,
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parms, flows, resolve_priority_neon);
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}
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}
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/*
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* Process 4 transitions (in 2 NEON Q registers) in parallel
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*/
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static __rte_always_inline int32x4_t
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transition4(int32x4_t next_input, const uint64_t *trans, uint64_t transitions[])
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{
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int32x4x2_t tr_hi_lo;
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int32x4_t t, in, r;
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uint32x4_t index_msk, node_type, addr;
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uint32x4_t dfa_msk, mask, quad_ofs, dfa_ofs;
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/* Move low 32 into tr_hi_lo.val[0] and high 32 into tr_hi_lo.val[1] */
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tr_hi_lo = vld2q_s32((const int32_t *)transitions);
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/* Calculate the address (array index) for all 4 transitions. */
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index_msk = vld1q_u32((const uint32_t *)&neon_acl_const.xmm_index_mask);
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/* Calc node type and node addr */
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node_type = vbicq_s32(tr_hi_lo.val[0], index_msk);
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addr = vandq_s32(tr_hi_lo.val[0], index_msk);
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/* t = 0 */
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t = veorq_s32(node_type, node_type);
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/* mask for DFA type(0) nodes */
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dfa_msk = vceqq_u32(node_type, t);
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mask = vld1q_s32((const int32_t *)&neon_acl_const.xmm_shuffle_input);
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in = vqtbl1q_u8((uint8x16_t)next_input, (uint8x16_t)mask);
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/* DFA calculations. */
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r = vshrq_n_u32(in, 30); /* div by 64 */
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mask = vld1q_s32((const int32_t *)&neon_acl_const.range_base);
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r = vaddq_u8(r, mask);
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t = vshrq_n_u32(in, 24);
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r = vqtbl1q_u8((uint8x16_t)tr_hi_lo.val[1], (uint8x16_t)r);
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dfa_ofs = vsubq_s32(t, r);
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/* QUAD/SINGLE calculations. */
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t = vcgtq_s8(in, tr_hi_lo.val[1]);
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t = vabsq_s8(t);
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t = vpaddlq_u8(t);
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quad_ofs = vpaddlq_u16(t);
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/* blend DFA and QUAD/SINGLE. */
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t = vbslq_u8(dfa_msk, dfa_ofs, quad_ofs);
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/* calculate address for next transitions */
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addr = vaddq_u32(addr, t);
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/* Fill next transitions */
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transitions[0] = trans[vgetq_lane_u32(addr, 0)];
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transitions[1] = trans[vgetq_lane_u32(addr, 1)];
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transitions[2] = trans[vgetq_lane_u32(addr, 2)];
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transitions[3] = trans[vgetq_lane_u32(addr, 3)];
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return vshrq_n_u32(next_input, CHAR_BIT);
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}
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/*
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* Execute trie traversal with 8 traversals in parallel
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*/
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static inline int
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search_neon_8(const struct rte_acl_ctx *ctx, const uint8_t **data,
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uint32_t *results, uint32_t total_packets, uint32_t categories)
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{
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int n;
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struct acl_flow_data flows;
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uint64_t index_array[8];
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struct completion cmplt[8];
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struct parms parms[8];
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int32x4_t input0, input1;
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acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,
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total_packets, categories, ctx->trans_table);
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for (n = 0; n < 8; n++) {
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cmplt[n].count = 0;
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index_array[n] = acl_start_next_trie(&flows, parms, n, ctx);
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}
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/* Check for any matches. */
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acl_match_check_x4(0, ctx, parms, &flows, &index_array[0]);
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acl_match_check_x4(4, ctx, parms, &flows, &index_array[4]);
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while (flows.started > 0) {
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/* Gather 4 bytes of input data for each stream. */
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input0 = vdupq_n_s32(GET_NEXT_4BYTES(parms, 0));
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input1 = vdupq_n_s32(GET_NEXT_4BYTES(parms, 4));
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input0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input0, 1);
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input1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 5), input1, 1);
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input0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 2), input0, 2);
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input1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 6), input1, 2);
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input0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 3), input0, 3);
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input1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 7), input1, 3);
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/* Process the 4 bytes of input on each stream. */
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input0 = transition4(input0, flows.trans, &index_array[0]);
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input1 = transition4(input1, flows.trans, &index_array[4]);
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input0 = transition4(input0, flows.trans, &index_array[0]);
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input1 = transition4(input1, flows.trans, &index_array[4]);
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input0 = transition4(input0, flows.trans, &index_array[0]);
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input1 = transition4(input1, flows.trans, &index_array[4]);
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input0 = transition4(input0, flows.trans, &index_array[0]);
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input1 = transition4(input1, flows.trans, &index_array[4]);
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/* Check for any matches. */
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acl_match_check_x4(0, ctx, parms, &flows, &index_array[0]);
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acl_match_check_x4(4, ctx, parms, &flows, &index_array[4]);
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}
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return 0;
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}
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/*
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* Execute trie traversal with 4 traversals in parallel
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*/
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static inline int
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search_neon_4(const struct rte_acl_ctx *ctx, const uint8_t **data,
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uint32_t *results, int total_packets, uint32_t categories)
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{
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int n;
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struct acl_flow_data flows;
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uint64_t index_array[4];
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struct completion cmplt[4];
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struct parms parms[4];
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int32x4_t input;
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acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,
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total_packets, categories, ctx->trans_table);
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for (n = 0; n < 4; n++) {
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cmplt[n].count = 0;
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index_array[n] = acl_start_next_trie(&flows, parms, n, ctx);
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}
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/* Check for any matches. */
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acl_match_check_x4(0, ctx, parms, &flows, index_array);
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while (flows.started > 0) {
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/* Gather 4 bytes of input data for each stream. */
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input = vdupq_n_s32(GET_NEXT_4BYTES(parms, 0));
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input = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input, 1);
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input = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 2), input, 2);
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input = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 3), input, 3);
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/* Process the 4 bytes of input on each stream. */
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input = transition4(input, flows.trans, index_array);
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input = transition4(input, flows.trans, index_array);
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input = transition4(input, flows.trans, index_array);
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input = transition4(input, flows.trans, index_array);
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/* Check for any matches. */
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acl_match_check_x4(0, ctx, parms, &flows, index_array);
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}
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return 0;
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}
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