2786b7bf90
When secondary process starts, it will allocate its own process private data, and also does remap to UAR register of the Tx queue. Once the secondary process exits, these resources should be released accordingly. And the shared resources owned by primary should not be touched. Currently, once one port in the secondary process spawn failed, all the other spawned ports will also be released during process exits. However, the mlx5_dev_close() function does not add the cases for secondary process, it means call the mlx5_dev_close() function directly in secondary process releases the resources it should not touch. Add the case for secondary process release to its own resources in mlx5_dev_close() function to help it quits gracefully. Fixes:942d13e6e7("net/mlx5: fix sharing context destroy order") Fixes:3a8207423a("net/mlx5: close all ports on remove") Cc: stable@dpdk.org Signed-off-by: Suanming Mou <suanmingm@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
685 lines
24 KiB
C
685 lines
24 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_RXTX_H_
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#define RTE_PMD_MLX5_RXTX_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#include <infiniband/mlx5dv.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_common.h>
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#include <rte_hexdump.h>
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#include <rte_atomic.h>
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#include <rte_spinlock.h>
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#include <rte_io.h>
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#include <rte_bus_pci.h>
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#include <rte_malloc.h>
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#include <mlx5_glue.h>
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#include <mlx5_prm.h>
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#include <mlx5_common.h>
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#include <mlx5_common_mr.h>
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#include "mlx5_defs.h"
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#include "mlx5_utils.h"
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#include "mlx5.h"
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#include "mlx5_autoconf.h"
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/* Support tunnel matching. */
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#define MLX5_FLOW_TUNNEL 10
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/* Mbuf dynamic flag offset for inline. */
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extern uint64_t rte_net_mlx5_dynf_inline_mask;
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struct mlx5_rxq_stats {
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t ipackets; /**< Total of successfully received packets. */
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uint64_t ibytes; /**< Total of successfully received bytes. */
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#endif
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uint64_t idropped; /**< Total of packets dropped when RX ring full. */
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uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
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};
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struct mlx5_txq_stats {
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#ifdef MLX5_PMD_SOFT_COUNTERS
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uint64_t opackets; /**< Total of successfully sent packets. */
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uint64_t obytes; /**< Total of successfully sent bytes. */
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#endif
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uint64_t oerrors; /**< Total number of failed transmitted packets. */
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};
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struct mlx5_priv;
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/* Compressed CQE context. */
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struct rxq_zip {
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uint16_t ai; /* Array index. */
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uint16_t ca; /* Current array index. */
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uint16_t na; /* Next array index. */
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uint16_t cq_ci; /* The next CQE. */
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uint32_t cqe_cnt; /* Number of CQEs. */
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};
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/* Multi-Packet RQ buffer header. */
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struct mlx5_mprq_buf {
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struct rte_mempool *mp;
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rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
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uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
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struct rte_mbuf_ext_shared_info shinfos[];
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/*
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* Shared information per stride.
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* More memory will be allocated for the first stride head-room and for
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* the strides data.
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*/
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} __rte_cache_aligned;
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/* Get pointer to the first stride. */
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#define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
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sizeof(struct mlx5_mprq_buf) + \
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(strd_n) * \
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sizeof(struct rte_mbuf_ext_shared_info) + \
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RTE_PKTMBUF_HEADROOM))
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#define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
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#define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
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enum mlx5_rxq_err_state {
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MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
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MLX5_RXQ_ERR_STATE_NEED_RESET,
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MLX5_RXQ_ERR_STATE_NEED_READY,
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};
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/* RX queue descriptor. */
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struct mlx5_rxq_data {
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unsigned int csum:1; /* Enable checksum offloading. */
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unsigned int hw_timestamp:1; /* Enable HW timestamp. */
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unsigned int vlan_strip:1; /* Enable VLAN stripping. */
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unsigned int crc_present:1; /* CRC must be subtracted. */
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unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
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unsigned int cqe_n:4; /* Log 2 of CQ elements. */
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unsigned int elts_n:4; /* Log 2 of Mbufs. */
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unsigned int rss_hash:1; /* RSS hash result is enabled. */
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unsigned int mark:1; /* Marked flow available on the queue. */
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unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
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unsigned int strd_sz_n:4; /* Log 2 of stride size. */
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unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
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unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
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unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
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unsigned int lro:1; /* Enable LRO. */
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unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
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volatile uint32_t *rq_db;
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volatile uint32_t *cq_db;
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uint16_t port_id;
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uint32_t rq_ci;
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uint16_t consumed_strd; /* Number of consumed strides in WQE. */
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uint32_t rq_pi;
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uint32_t cq_ci;
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uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
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union {
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struct rxq_zip zip; /* Compressed context. */
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uint16_t decompressed;
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/* Number of ready mbufs decompressed from the CQ. */
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};
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struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
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uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
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volatile void *wqes;
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volatile struct mlx5_cqe(*cqes)[];
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RTE_STD_C11
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union {
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struct rte_mbuf *(*elts)[];
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struct mlx5_mprq_buf *(*mprq_bufs)[];
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};
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struct rte_mempool *mp;
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struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
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struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
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uint16_t idx; /* Queue index. */
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struct mlx5_rxq_stats stats;
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rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
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struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
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void *cq_uar; /* CQ user access region. */
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uint32_t cqn; /* CQ number. */
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uint8_t cq_arm_sn; /* CQ arm seq number. */
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#ifndef RTE_ARCH_64
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rte_spinlock_t *uar_lock_cq;
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/* CQ (UAR) access lock required for 32bit implementations */
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#endif
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uint32_t tunnel; /* Tunnel information. */
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uint64_t flow_meta_mask;
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int32_t flow_meta_offset;
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} __rte_cache_aligned;
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enum mlx5_rxq_obj_type {
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MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
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MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
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MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
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/* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
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};
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enum mlx5_rxq_type {
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MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
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MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
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MLX5_RXQ_TYPE_UNDEFINED,
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};
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/* Verbs/DevX Rx queue elements. */
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struct mlx5_rxq_obj {
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LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
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struct ibv_cq *cq; /* Completion Queue. */
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enum mlx5_rxq_obj_type type;
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RTE_STD_C11
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union {
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struct ibv_wq *wq; /* Work Queue. */
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struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
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};
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struct ibv_comp_channel *channel;
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};
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/* RX queue control descriptor. */
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struct mlx5_rxq_ctrl {
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struct mlx5_rxq_data rxq; /* Data path structure. */
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LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
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struct mlx5_priv *priv; /* Back pointer to private data. */
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enum mlx5_rxq_type type; /* Rxq type. */
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unsigned int socket; /* CPU socket ID for allocations. */
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unsigned int irq:1; /* Whether IRQ is enabled. */
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unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
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uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
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uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
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uint32_t wqn; /* WQ number. */
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uint16_t dump_file_n; /* Number of dump files. */
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uint32_t dbr_umem_id; /* Storing door-bell information, */
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uint64_t dbr_offset; /* needed when freeing door-bell. */
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struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
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struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
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};
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enum mlx5_ind_tbl_type {
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MLX5_IND_TBL_TYPE_IBV,
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MLX5_IND_TBL_TYPE_DEVX,
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};
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/* Indirection table. */
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struct mlx5_ind_table_obj {
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LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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enum mlx5_ind_tbl_type type;
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RTE_STD_C11
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union {
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struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
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struct mlx5_devx_obj *rqt; /* DevX RQT object. */
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};
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uint32_t queues_n; /**< Number of queues in the list. */
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uint16_t queues[]; /**< Queue list. */
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};
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/* Hash Rx queue. */
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struct mlx5_hrxq {
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ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
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RTE_STD_C11
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union {
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struct ibv_qp *qp; /* Verbs queue pair. */
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struct mlx5_devx_obj *tir; /* DevX TIR object. */
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};
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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void *action; /* DV QP action pointer. */
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#endif
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uint64_t hash_fields; /* Verbs Hash fields. */
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uint32_t rss_key_len; /* Hash key length in bytes. */
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uint8_t rss_key[]; /* Hash key. */
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};
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/* TX queue send local data. */
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__extension__
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struct mlx5_txq_local {
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struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
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struct rte_mbuf *mbuf; /* first mbuf to process. */
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uint16_t pkts_copy; /* packets copied to elts. */
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uint16_t pkts_sent; /* packets sent. */
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uint16_t pkts_loop; /* packets sent on loop entry. */
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uint16_t elts_free; /* available elts remain. */
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uint16_t wqe_free; /* available wqe remain. */
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uint16_t mbuf_off; /* data offset in current mbuf. */
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uint16_t mbuf_nseg; /* number of remaining mbuf. */
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};
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/* TX queue descriptor. */
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__extension__
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struct mlx5_txq_data {
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uint16_t elts_head; /* Current counter in (*elts)[]. */
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uint16_t elts_tail; /* Counter of first element awaiting completion. */
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uint16_t elts_comp; /* elts index since last completion request. */
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uint16_t elts_s; /* Number of mbuf elements. */
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uint16_t elts_m; /* Mask for mbuf elements indices. */
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/* Fields related to elts mbuf storage. */
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uint16_t wqe_ci; /* Consumer index for work queue. */
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uint16_t wqe_pi; /* Producer index for work queue. */
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uint16_t wqe_s; /* Number of WQ elements. */
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uint16_t wqe_m; /* Mask Number for WQ elements. */
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uint16_t wqe_comp; /* WQE index since last completion request. */
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uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
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/* WQ related fields. */
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uint16_t cq_ci; /* Consumer index for completion queue. */
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uint16_t cq_pi; /* Production index for completion queue. */
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uint16_t cqe_s; /* Number of CQ elements. */
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uint16_t cqe_m; /* Mask for CQ indices. */
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/* CQ related fields. */
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uint16_t elts_n:4; /* elts[] length (in log2). */
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uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
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uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
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uint16_t tso_en:1; /* When set hardware TSO is enabled. */
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uint16_t tunnel_en:1;
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/* When set TX offload for tunneled packets are supported. */
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uint16_t swp_en:1; /* Whether SW parser is enabled. */
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uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
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uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
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uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
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uint16_t inlen_send; /* Ordinary send data inline size. */
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uint16_t inlen_empw; /* eMPW max packet size to inline. */
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uint16_t inlen_mode; /* Minimal data length to inline. */
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uint32_t qp_num_8s; /* QP number shifted by 8. */
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uint64_t offloads; /* Offloads for Tx Queue. */
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struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
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struct mlx5_wqe *wqes; /* Work queue. */
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struct mlx5_wqe *wqes_end; /* Work queue array limit. */
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#ifdef RTE_LIBRTE_MLX5_DEBUG
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uint32_t *fcqs; /* Free completion queue (debug extended). */
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#else
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uint16_t *fcqs; /* Free completion queue. */
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#endif
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volatile struct mlx5_cqe *cqes; /* Completion queue. */
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volatile uint32_t *qp_db; /* Work queue doorbell. */
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volatile uint32_t *cq_db; /* Completion queue doorbell. */
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uint16_t port_id; /* Port ID of device. */
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uint16_t idx; /* Queue index. */
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struct mlx5_txq_stats stats; /* TX queue counters. */
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#ifndef RTE_ARCH_64
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rte_spinlock_t *uar_lock;
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/* UAR access lock required for 32bit implementations */
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#endif
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struct rte_mbuf *elts[0];
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/* Storage for queued packets, must be the last field. */
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} __rte_cache_aligned;
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enum mlx5_txq_obj_type {
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MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
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MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
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/* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
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};
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enum mlx5_txq_type {
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MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
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MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
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};
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/* Verbs/DevX Tx queue elements. */
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struct mlx5_txq_obj {
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LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
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enum mlx5_txq_obj_type type; /* The txq object type. */
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RTE_STD_C11
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union {
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struct {
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struct ibv_cq *cq; /* Completion Queue. */
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struct ibv_qp *qp; /* Queue Pair. */
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};
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struct {
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struct mlx5_devx_obj *sq;
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/* DevX object for Sx queue. */
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struct mlx5_devx_obj *tis; /* The TIS object. */
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};
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};
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};
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/* TX queue control descriptor. */
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struct mlx5_txq_ctrl {
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LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
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rte_atomic32_t refcnt; /* Reference counter. */
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unsigned int socket; /* CPU socket ID for allocations. */
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enum mlx5_txq_type type; /* The txq ctrl type. */
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unsigned int max_inline_data; /* Max inline data. */
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unsigned int max_tso_header; /* Max TSO header size. */
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struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
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struct mlx5_priv *priv; /* Back pointer to private data. */
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off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
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void *bf_reg; /* BlueFlame register from Verbs. */
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uint16_t dump_file_n; /* Number of dump files. */
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struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
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struct mlx5_txq_data txq; /* Data path structure. */
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/* Must be the last field in the structure, contains elts[]. */
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};
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#define MLX5_TX_BFREG(txq) \
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(MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
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/* mlx5_rxq.c */
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extern uint8_t rss_hash_default_key[];
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int mlx5_check_mprq_support(struct rte_eth_dev *dev);
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int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
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int mlx5_mprq_enabled(struct rte_eth_dev *dev);
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int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
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int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
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int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
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unsigned int socket, const struct rte_eth_rxconf *conf,
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struct rte_mempool *mp);
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int mlx5_rx_hairpin_queue_setup
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(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
|
|
const struct rte_eth_hairpin_conf *hairpin_conf);
|
|
void mlx5_rx_queue_release(void *dpdk_rxq);
|
|
int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
|
|
void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
|
|
int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
|
|
int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
|
|
struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
|
|
enum mlx5_rxq_obj_type type);
|
|
int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
|
|
struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
|
|
uint16_t desc, unsigned int socket,
|
|
const struct rte_eth_rxconf *conf,
|
|
struct rte_mempool *mp);
|
|
struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
|
|
(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
|
|
const struct rte_eth_hairpin_conf *hairpin_conf);
|
|
struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_rxq_verify(struct rte_eth_dev *dev);
|
|
int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
|
|
int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
|
|
uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,
|
|
const uint8_t *rss_key, uint32_t rss_key_len,
|
|
uint64_t hash_fields,
|
|
const uint16_t *queues, uint32_t queues_n,
|
|
int tunnel __rte_unused);
|
|
uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
|
|
const uint8_t *rss_key, uint32_t rss_key_len,
|
|
uint64_t hash_fields,
|
|
const uint16_t *queues, uint32_t queues_n);
|
|
int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
|
|
int mlx5_hrxq_verify(struct rte_eth_dev *dev);
|
|
enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
|
|
struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
|
|
void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
|
|
uint64_t mlx5_get_rx_port_offloads(void);
|
|
uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
|
|
|
|
/* mlx5_txq.c */
|
|
|
|
int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
|
|
unsigned int socket, const struct rte_eth_txconf *conf);
|
|
int mlx5_tx_hairpin_queue_setup
|
|
(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
|
|
const struct rte_eth_hairpin_conf *hairpin_conf);
|
|
void mlx5_tx_queue_release(void *dpdk_txq);
|
|
int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
|
|
void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
|
|
struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
|
|
enum mlx5_txq_obj_type type);
|
|
struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
|
|
int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
|
|
struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
|
|
uint16_t desc, unsigned int socket,
|
|
const struct rte_eth_txconf *conf);
|
|
struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
|
|
(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
|
|
const struct rte_eth_hairpin_conf *hairpin_conf);
|
|
struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
|
|
int mlx5_txq_verify(struct rte_eth_dev *dev);
|
|
void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
|
|
void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
|
|
uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
|
|
|
|
/* mlx5_rxtx.c */
|
|
|
|
extern uint32_t mlx5_ptype_table[];
|
|
extern uint8_t mlx5_cksum_table[];
|
|
extern uint8_t mlx5_swp_types_table[];
|
|
|
|
void mlx5_set_ptype_table(void);
|
|
void mlx5_set_cksum_table(void);
|
|
void mlx5_set_swp_types_table(void);
|
|
uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
|
|
void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
|
|
__rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
|
|
void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
|
|
void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
|
|
uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
|
|
uint16_t pkts_n);
|
|
uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
|
|
uint16_t pkts_n);
|
|
uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
|
|
uint16_t pkts_n);
|
|
int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
|
|
int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
|
|
uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
|
|
void mlx5_dump_debug_information(const char *path, const char *title,
|
|
const void *buf, unsigned int len);
|
|
int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
|
|
const struct mlx5_mp_arg_queue_state_modify *sm);
|
|
void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
|
|
struct rte_eth_rxq_info *qinfo);
|
|
void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
|
|
struct rte_eth_txq_info *qinfo);
|
|
int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
|
|
struct rte_eth_burst_mode *mode);
|
|
int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
|
|
struct rte_eth_burst_mode *mode);
|
|
|
|
/* Vectorized version of mlx5_rxtx.c */
|
|
int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
|
|
int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
|
|
uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
|
|
uint16_t pkts_n);
|
|
|
|
/* mlx5_mr.c */
|
|
|
|
void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
|
|
uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
|
|
uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
|
|
uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
|
|
struct rte_mempool *mp);
|
|
int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
|
|
size_t len);
|
|
int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
|
|
size_t len);
|
|
|
|
/**
|
|
* Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
|
|
* 64bit architectures.
|
|
*
|
|
* @param val
|
|
* value to write in CPU endian format.
|
|
* @param addr
|
|
* Address to write to.
|
|
* @param lock
|
|
* Address of the lock to use for that UAR access.
|
|
*/
|
|
static __rte_always_inline void
|
|
__mlx5_uar_write64_relaxed(uint64_t val, void *addr,
|
|
rte_spinlock_t *lock __rte_unused)
|
|
{
|
|
#ifdef RTE_ARCH_64
|
|
*(uint64_t *)addr = val;
|
|
#else /* !RTE_ARCH_64 */
|
|
rte_spinlock_lock(lock);
|
|
*(uint32_t *)addr = val;
|
|
rte_io_wmb();
|
|
*((uint32_t *)addr + 1) = val >> 32;
|
|
rte_spinlock_unlock(lock);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
|
|
* 64bit architectures while guaranteeing the order of execution with the
|
|
* code being executed.
|
|
*
|
|
* @param val
|
|
* value to write in CPU endian format.
|
|
* @param addr
|
|
* Address to write to.
|
|
* @param lock
|
|
* Address of the lock to use for that UAR access.
|
|
*/
|
|
static __rte_always_inline void
|
|
__mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
|
|
{
|
|
rte_io_wmb();
|
|
__mlx5_uar_write64_relaxed(val, addr, lock);
|
|
}
|
|
|
|
/* Assist macros, used instead of directly calling the functions they wrap. */
|
|
#ifdef RTE_ARCH_64
|
|
#define mlx5_uar_write64_relaxed(val, dst, lock) \
|
|
__mlx5_uar_write64_relaxed(val, dst, NULL)
|
|
#define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
|
|
#else
|
|
#define mlx5_uar_write64_relaxed(val, dst, lock) \
|
|
__mlx5_uar_write64_relaxed(val, dst, lock)
|
|
#define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
|
|
#endif
|
|
|
|
/**
|
|
* Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
|
|
* cloned mbuf is allocated is returned instead.
|
|
*
|
|
* @param buf
|
|
* Pointer to mbuf.
|
|
*
|
|
* @return
|
|
* Memory pool where data is located for given mbuf.
|
|
*/
|
|
static inline struct rte_mempool *
|
|
mlx5_mb2mp(struct rte_mbuf *buf)
|
|
{
|
|
if (unlikely(RTE_MBUF_CLONED(buf)))
|
|
return rte_mbuf_from_indirect(buf)->pool;
|
|
return buf->pool;
|
|
}
|
|
|
|
/**
|
|
* Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
|
|
* as mempool is pre-configured and static.
|
|
*
|
|
* @param rxq
|
|
* Pointer to Rx queue structure.
|
|
* @param addr
|
|
* Address to search.
|
|
*
|
|
* @return
|
|
* Searched LKey on success, UINT32_MAX on no match.
|
|
*/
|
|
static __rte_always_inline uint32_t
|
|
mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
|
|
{
|
|
struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
|
|
uint32_t lkey;
|
|
|
|
/* Linear search on MR cache array. */
|
|
lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
|
|
MLX5_MR_CACHE_N, addr);
|
|
if (likely(lkey != UINT32_MAX))
|
|
return lkey;
|
|
/* Take slower bottom-half (Binary Search) on miss. */
|
|
return mlx5_rx_addr2mr_bh(rxq, addr);
|
|
}
|
|
|
|
#define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
|
|
|
|
/**
|
|
* Query LKey from a packet buffer for Tx. If not found, add the mempool.
|
|
*
|
|
* @param txq
|
|
* Pointer to Tx queue structure.
|
|
* @param addr
|
|
* Address to search.
|
|
*
|
|
* @return
|
|
* Searched LKey on success, UINT32_MAX on no match.
|
|
*/
|
|
static __rte_always_inline uint32_t
|
|
mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
|
|
{
|
|
struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
|
|
uintptr_t addr = (uintptr_t)mb->buf_addr;
|
|
uint32_t lkey;
|
|
|
|
/* Check generation bit to see if there's any change on existing MRs. */
|
|
if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
|
|
mlx5_mr_flush_local_cache(mr_ctrl);
|
|
/* Linear search on MR cache array. */
|
|
lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
|
|
MLX5_MR_CACHE_N, addr);
|
|
if (likely(lkey != UINT32_MAX))
|
|
return lkey;
|
|
/* Take slower bottom-half on miss. */
|
|
return mlx5_tx_mb2mr_bh(txq, mb);
|
|
}
|
|
|
|
/**
|
|
* Ring TX queue doorbell and flush the update if requested.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param wqe
|
|
* Pointer to the last WQE posted in the NIC.
|
|
* @param cond
|
|
* Request for write memory barrier after BlueFlame update.
|
|
*/
|
|
static __rte_always_inline void
|
|
mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
|
|
int cond)
|
|
{
|
|
uint64_t *dst = MLX5_TX_BFREG(txq);
|
|
volatile uint64_t *src = ((volatile uint64_t *)wqe);
|
|
|
|
rte_cio_wmb();
|
|
*txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
|
|
/* Ensure ordering between DB record and BF copy. */
|
|
rte_wmb();
|
|
mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
|
|
if (cond)
|
|
rte_wmb();
|
|
}
|
|
|
|
/**
|
|
* Ring TX queue doorbell and flush the update by write memory barrier.
|
|
*
|
|
* @param txq
|
|
* Pointer to TX queue structure.
|
|
* @param wqe
|
|
* Pointer to the last WQE posted in the NIC.
|
|
*/
|
|
static __rte_always_inline void
|
|
mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
|
|
{
|
|
mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
|
|
}
|
|
|
|
#endif /* RTE_PMD_MLX5_RXTX_H_ */
|