37a725d66d
Support for re-configuration of number of queues per port and descriptor size. Renamed variable representing number of descriptors as nb_desc from max_count. Signed-off-by: Shijith Thotton <shijith.thotton@caviumnetworks.com>
514 lines
13 KiB
C
514 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Cavium, Inc
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*/
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#include <string.h>
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#include <rte_ethdev.h>
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#include <rte_cycles.h>
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#include <rte_malloc.h>
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#include "lio_logs.h"
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#include "lio_23xx_vf.h"
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#include "lio_23xx_reg.h"
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#include "lio_mbox.h"
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static int
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cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
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{
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uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
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uint64_t d64, q_no;
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int ret_val = 0;
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PMD_INIT_FUNC_TRACE();
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for (q_no = 0; q_no < num_queues; q_no++) {
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/* set RST bit to 1. This bit applies to both IQ and OQ */
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d64 = lio_read_csr64(lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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d64);
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}
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/* wait until the RST bit is clear or the RST and QUIET bits are set */
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for (q_no = 0; q_no < num_queues; q_no++) {
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volatile uint64_t reg_val;
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reg_val = lio_read_csr64(lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
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!(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
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loop) {
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reg_val = lio_read_csr64(
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lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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loop = loop - 1;
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}
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if (loop == 0) {
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lio_dev_err(lio_dev,
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"clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
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(unsigned long)q_no);
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return -1;
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}
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reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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reg_val);
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reg_val = lio_read_csr64(
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lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
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lio_dev_err(lio_dev,
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"clearing the reset failed for qno: %lu\n",
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(unsigned long)q_no);
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ret_val = -1;
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}
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}
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return ret_val;
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}
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static int
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cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
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{
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uint64_t q_no;
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uint64_t d64;
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PMD_INIT_FUNC_TRACE();
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if (cn23xx_vf_reset_io_queues(lio_dev,
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lio_dev->sriov_info.rings_per_vf))
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return -1;
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for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
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0xFFFFFFFF);
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d64 = lio_read_csr64(lio_dev,
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CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
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d64 &= 0xEFFFFFFFFFFFFFFFL;
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
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d64);
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/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
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* the Input Queues
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*/
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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CN23XX_PKT_INPUT_CTL_MASK);
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}
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return 0;
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}
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static void
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cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
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{
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uint32_t reg_val;
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uint32_t q_no;
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PMD_INIT_FUNC_TRACE();
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for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
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lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
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0xFFFFFFFF);
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reg_val =
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lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
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reg_val &= 0xEFFFFFFFFFFFFFFFL;
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lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no), reg_val);
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reg_val =
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lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
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/* set IPTR & DPTR */
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reg_val |=
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(CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
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/* reset BMODE */
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue Scatter List
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* reset ROR_P, NSR_P
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
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#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
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#endif
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue Data
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* reset ROR, NSR
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
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/* set the ES bit */
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
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/* write all the selected settings */
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lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
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reg_val);
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}
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}
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static int
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cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
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{
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PMD_INIT_FUNC_TRACE();
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if (cn23xx_vf_setup_global_input_regs(lio_dev))
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return -1;
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cn23xx_vf_setup_global_output_regs(lio_dev);
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return 0;
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}
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static void
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cn23xx_vf_setup_iq_regs(struct lio_device *lio_dev, uint32_t iq_no)
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{
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struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no];
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uint64_t pkt_in_done = 0;
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PMD_INIT_FUNC_TRACE();
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/* Write the start of the input queue's ring and its size */
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lio_write_csr64(lio_dev, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
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iq->base_addr_dma);
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lio_write_csr(lio_dev, CN23XX_SLI_IQ_SIZE(iq_no), iq->nb_desc);
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/* Remember the doorbell & instruction count register addr
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* for this queue
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*/
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iq->doorbell_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_IQ_DOORBELL(iq_no);
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iq->inst_cnt_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
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lio_dev_dbg(lio_dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
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iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
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/* Store the current instruction counter (used in flush_iq
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* calculation)
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*/
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pkt_in_done = rte_read64(iq->inst_cnt_reg);
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/* Clear the count by writing back what we read, but don't
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* enable data traffic here
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*/
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rte_write64(pkt_in_done, iq->inst_cnt_reg);
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}
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static void
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cn23xx_vf_setup_oq_regs(struct lio_device *lio_dev, uint32_t oq_no)
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{
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struct lio_droq *droq = lio_dev->droq[oq_no];
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PMD_INIT_FUNC_TRACE();
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lio_write_csr64(lio_dev, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
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droq->desc_ring_dma);
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lio_write_csr(lio_dev, CN23XX_SLI_OQ_SIZE(oq_no), droq->nb_desc);
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lio_write_csr(lio_dev, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
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(droq->buffer_size | (OCTEON_RH_SIZE << 16)));
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/* Get the mapped address of the pkt_sent and pkts_credit regs */
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droq->pkts_sent_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_OQ_PKTS_SENT(oq_no);
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droq->pkts_credit_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
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}
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static void
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cn23xx_vf_free_mbox(struct lio_device *lio_dev)
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{
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PMD_INIT_FUNC_TRACE();
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rte_free(lio_dev->mbox[0]);
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lio_dev->mbox[0] = NULL;
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rte_free(lio_dev->mbox);
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lio_dev->mbox = NULL;
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}
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static int
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cn23xx_vf_setup_mbox(struct lio_device *lio_dev)
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{
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struct lio_mbox *mbox;
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PMD_INIT_FUNC_TRACE();
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if (lio_dev->mbox == NULL) {
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lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0);
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if (lio_dev->mbox == NULL)
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return -ENOMEM;
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}
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mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0);
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if (mbox == NULL) {
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rte_free(lio_dev->mbox);
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lio_dev->mbox = NULL;
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return -ENOMEM;
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}
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rte_spinlock_init(&mbox->lock);
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mbox->lio_dev = lio_dev;
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mbox->q_no = 0;
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mbox->state = LIO_MBOX_STATE_IDLE;
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/* VF mbox interrupt reg */
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mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_VF_SLI_PKT_MBOX_INT(0);
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/* VF reads from SIG0 reg */
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mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
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/* VF writes into SIG1 reg */
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mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr +
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CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
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lio_dev->mbox[0] = mbox;
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rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg);
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return 0;
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}
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static int
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cn23xx_vf_enable_io_queues(struct lio_device *lio_dev)
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{
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uint32_t q_no;
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PMD_INIT_FUNC_TRACE();
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for (q_no = 0; q_no < lio_dev->num_iqs; q_no++) {
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uint64_t reg_val;
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/* set the corresponding IQ IS_64B bit */
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if (lio_dev->io_qmask.iq64B & (1ULL << q_no)) {
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reg_val = lio_read_csr64(
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lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
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lio_write_csr64(lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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reg_val);
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}
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/* set the corresponding IQ ENB bit */
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if (lio_dev->io_qmask.iq & (1ULL << q_no)) {
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reg_val = lio_read_csr64(
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lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
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lio_write_csr64(lio_dev,
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CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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reg_val);
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}
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}
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for (q_no = 0; q_no < lio_dev->num_oqs; q_no++) {
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uint32_t reg_val;
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/* set the corresponding OQ ENB bit */
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if (lio_dev->io_qmask.oq & (1ULL << q_no)) {
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reg_val = lio_read_csr(
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lio_dev,
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CN23XX_SLI_OQ_PKT_CONTROL(q_no));
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reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
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lio_write_csr(lio_dev,
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CN23XX_SLI_OQ_PKT_CONTROL(q_no),
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reg_val);
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}
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}
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return 0;
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}
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static void
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cn23xx_vf_disable_io_queues(struct lio_device *lio_dev)
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{
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uint32_t num_queues;
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PMD_INIT_FUNC_TRACE();
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/* per HRM, rings can only be disabled via reset operation,
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* NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB]
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*/
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num_queues = lio_dev->num_iqs;
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if (num_queues < lio_dev->num_oqs)
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num_queues = lio_dev->num_oqs;
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cn23xx_vf_reset_io_queues(lio_dev, num_queues);
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}
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void
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cn23xx_vf_ask_pf_to_do_flr(struct lio_device *lio_dev)
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{
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struct lio_mbox_cmd mbox_cmd;
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memset(&mbox_cmd, 0, sizeof(struct lio_mbox_cmd));
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mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
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mbox_cmd.msg.s.resp_needed = 0;
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mbox_cmd.msg.s.cmd = LIO_VF_FLR_REQUEST;
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mbox_cmd.msg.s.len = 1;
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mbox_cmd.q_no = 0;
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mbox_cmd.recv_len = 0;
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mbox_cmd.recv_status = 0;
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mbox_cmd.fn = NULL;
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mbox_cmd.fn_arg = 0;
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lio_mbox_write(lio_dev, &mbox_cmd);
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}
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static void
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cn23xx_pfvf_hs_callback(struct lio_device *lio_dev,
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struct lio_mbox_cmd *cmd, void *arg)
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{
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uint32_t major = 0;
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PMD_INIT_FUNC_TRACE();
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rte_memcpy((uint8_t *)&lio_dev->pfvf_hsword, cmd->msg.s.params, 6);
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if (cmd->recv_len > 1) {
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struct lio_version *lio_ver = (struct lio_version *)cmd->data;
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major = lio_ver->major;
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major = major << 16;
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}
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rte_atomic64_set((rte_atomic64_t *)arg, major | 1);
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}
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int
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cn23xx_pfvf_handshake(struct lio_device *lio_dev)
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{
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struct lio_mbox_cmd mbox_cmd;
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struct lio_version *lio_ver = (struct lio_version *)&mbox_cmd.data[0];
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uint32_t q_no, count = 0;
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rte_atomic64_t status;
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uint32_t pfmajor;
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uint32_t vfmajor;
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uint32_t ret;
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PMD_INIT_FUNC_TRACE();
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/* Sending VF_ACTIVE indication to the PF driver */
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lio_dev_dbg(lio_dev, "requesting info from PF\n");
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mbox_cmd.msg.mbox_msg64 = 0;
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mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
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mbox_cmd.msg.s.resp_needed = 1;
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mbox_cmd.msg.s.cmd = LIO_VF_ACTIVE;
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mbox_cmd.msg.s.len = 2;
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mbox_cmd.data[0] = 0;
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lio_ver->major = LIO_BASE_MAJOR_VERSION;
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lio_ver->minor = LIO_BASE_MINOR_VERSION;
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lio_ver->micro = LIO_BASE_MICRO_VERSION;
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mbox_cmd.q_no = 0;
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mbox_cmd.recv_len = 0;
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mbox_cmd.recv_status = 0;
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mbox_cmd.fn = (lio_mbox_callback)cn23xx_pfvf_hs_callback;
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mbox_cmd.fn_arg = (void *)&status;
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if (lio_mbox_write(lio_dev, &mbox_cmd)) {
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lio_dev_err(lio_dev, "Write to mailbox failed\n");
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return -1;
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}
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rte_atomic64_set(&status, 0);
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do {
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rte_delay_ms(1);
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} while ((rte_atomic64_read(&status) == 0) && (count++ < 10000));
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ret = rte_atomic64_read(&status);
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if (ret == 0) {
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lio_dev_err(lio_dev, "cn23xx_pfvf_handshake timeout\n");
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return -1;
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}
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for (q_no = 0; q_no < lio_dev->num_iqs; q_no++)
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lio_dev->instr_queue[q_no]->txpciq.s.pkind =
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lio_dev->pfvf_hsword.pkind;
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vfmajor = LIO_BASE_MAJOR_VERSION;
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pfmajor = ret >> 16;
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if (pfmajor != vfmajor) {
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lio_dev_err(lio_dev,
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"VF LiquidIO driver (major version %d) is not compatible with LiquidIO PF driver (major version %d)\n",
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vfmajor, pfmajor);
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ret = -EPERM;
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} else {
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lio_dev_dbg(lio_dev,
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"VF LiquidIO driver (major version %d), LiquidIO PF driver (major version %d)\n",
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vfmajor, pfmajor);
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ret = 0;
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}
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lio_dev_dbg(lio_dev, "got data from PF pkind is %d\n",
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lio_dev->pfvf_hsword.pkind);
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return ret;
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}
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|
|
|
void
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|
cn23xx_vf_handle_mbox(struct lio_device *lio_dev)
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|
{
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|
uint64_t mbox_int_val;
|
|
|
|
/* read and clear by writing 1 */
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|
mbox_int_val = rte_read64(lio_dev->mbox[0]->mbox_int_reg);
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|
rte_write64(mbox_int_val, lio_dev->mbox[0]->mbox_int_reg);
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|
if (lio_mbox_read(lio_dev->mbox[0]))
|
|
lio_mbox_process_message(lio_dev->mbox[0]);
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|
}
|
|
|
|
int
|
|
cn23xx_vf_setup_device(struct lio_device *lio_dev)
|
|
{
|
|
uint64_t reg_val;
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
/* INPUT_CONTROL[RPVF] gives the VF IOq count */
|
|
reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
|
|
|
|
lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
|
|
CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
|
|
lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
|
|
CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
|
|
|
|
reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
|
|
|
|
lio_dev->sriov_info.rings_per_vf =
|
|
reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
|
|
|
|
lio_dev->default_config = lio_get_conf(lio_dev);
|
|
if (lio_dev->default_config == NULL)
|
|
return -1;
|
|
|
|
lio_dev->fn_list.setup_iq_regs = cn23xx_vf_setup_iq_regs;
|
|
lio_dev->fn_list.setup_oq_regs = cn23xx_vf_setup_oq_regs;
|
|
lio_dev->fn_list.setup_mbox = cn23xx_vf_setup_mbox;
|
|
lio_dev->fn_list.free_mbox = cn23xx_vf_free_mbox;
|
|
|
|
lio_dev->fn_list.setup_device_regs = cn23xx_vf_setup_device_regs;
|
|
|
|
lio_dev->fn_list.enable_io_queues = cn23xx_vf_enable_io_queues;
|
|
lio_dev->fn_list.disable_io_queues = cn23xx_vf_disable_io_queues;
|
|
|
|
return 0;
|
|
}
|
|
|