5045e2b25a
There are coverity defects related "Unintended sign extension" in the
internal static function named hns3_get_regs_length used for dumping reg
operation.
This patch fixes them by replacing the data type of cmdq_lines,
common_lines, ring_lines and tqp_intr_lines with uint32_t in the inner
static function named hns3_get_regs_length of hns3 PMD driver.
Coverity issue: 349917, 349914
Fixes: 936eda25e8 ("net/hns3: support dump register")
Cc: stable@dpdk.org
Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
376 lines
9.7 KiB
C
376 lines
9.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#include <errno.h>
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#include <stdarg.h>
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#include <stdbool.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include <rte_bus_pci.h>
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#include <rte_byteorder.h>
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#include <rte_common.h>
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#include <rte_dev.h>
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#include <rte_eal.h>
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#include <rte_ether.h>
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#include <rte_ethdev_driver.h>
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#include <rte_ethdev_pci.h>
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#include <rte_io.h>
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#include <rte_pci.h>
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#include "hns3_ethdev.h"
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#include "hns3_logs.h"
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#include "hns3_rxtx.h"
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#include "hns3_regs.h"
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#define MAX_SEPARATE_NUM 4
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#define SEPARATOR_VALUE 0xFFFFFFFF
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#define REG_NUM_PER_LINE 4
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#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(uint32_t))
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static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
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HNS3_CMDQ_TX_ADDR_H_REG,
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HNS3_CMDQ_TX_DEPTH_REG,
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HNS3_CMDQ_TX_TAIL_REG,
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HNS3_CMDQ_TX_HEAD_REG,
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HNS3_CMDQ_RX_ADDR_L_REG,
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HNS3_CMDQ_RX_ADDR_H_REG,
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HNS3_CMDQ_RX_DEPTH_REG,
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HNS3_CMDQ_RX_TAIL_REG,
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HNS3_CMDQ_RX_HEAD_REG,
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HNS3_VECTOR0_CMDQ_SRC_REG,
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HNS3_CMDQ_INTR_STS_REG,
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HNS3_CMDQ_INTR_EN_REG,
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HNS3_CMDQ_INTR_GEN_REG};
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static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
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HNS3_VECTOR0_OTER_EN_REG,
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HNS3_MISC_RESET_STS_REG,
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HNS3_VECTOR0_OTHER_INT_STS_REG,
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HNS3_GLOBAL_RESET_REG,
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HNS3_FUN_RST_ING,
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HNS3_GRO_EN_REG};
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static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
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HNS3_FUN_RST_ING,
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HNS3_GRO_EN_REG};
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static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
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HNS3_RING_RX_BASEADDR_H_REG,
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HNS3_RING_RX_BD_NUM_REG,
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HNS3_RING_RX_BD_LEN_REG,
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HNS3_RING_RX_MERGE_EN_REG,
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HNS3_RING_RX_TAIL_REG,
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HNS3_RING_RX_HEAD_REG,
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HNS3_RING_RX_FBDNUM_REG,
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HNS3_RING_RX_OFFSET_REG,
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HNS3_RING_RX_FBD_OFFSET_REG,
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HNS3_RING_RX_STASH_REG,
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HNS3_RING_RX_BD_ERR_REG,
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HNS3_RING_TX_BASEADDR_L_REG,
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HNS3_RING_TX_BASEADDR_H_REG,
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HNS3_RING_TX_BD_NUM_REG,
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HNS3_RING_TX_PRIORITY_REG,
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HNS3_RING_TX_TC_REG,
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HNS3_RING_TX_MERGE_EN_REG,
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HNS3_RING_TX_TAIL_REG,
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HNS3_RING_TX_HEAD_REG,
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HNS3_RING_TX_FBDNUM_REG,
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HNS3_RING_TX_OFFSET_REG,
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HNS3_RING_TX_EBD_NUM_REG,
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HNS3_RING_TX_EBD_OFFSET_REG,
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HNS3_RING_TX_BD_ERR_REG,
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HNS3_RING_EN_REG};
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static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
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HNS3_TQP_INTR_GL0_REG,
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HNS3_TQP_INTR_GL1_REG,
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HNS3_TQP_INTR_GL2_REG,
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HNS3_TQP_INTR_RL_REG};
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static int
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hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
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uint32_t *regs_num_64_bit)
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{
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struct hns3_cmd_desc desc;
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int ret;
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hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
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ret = hns3_cmd_send(hw, &desc, 1);
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if (ret) {
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hns3_err(hw, "Query register number cmd failed, ret = %d",
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ret);
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return ret;
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}
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*regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
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*regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
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return 0;
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}
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static int
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hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
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{
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struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
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uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
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uint32_t regs_num_32_bit, regs_num_64_bit;
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uint32_t len;
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int ret;
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cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
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if (hns->is_vf)
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common_lines =
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sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
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else
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common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
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ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
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tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
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len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
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tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE;
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if (!hns->is_vf) {
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ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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if (ret) {
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hns3_err(hw, "Get register number failed, ret = %d.",
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ret);
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return -ENOTSUP;
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}
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len += regs_num_32_bit * sizeof(uint32_t) +
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regs_num_64_bit * sizeof(uint64_t);
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}
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*length = len;
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return 0;
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}
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static int
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hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
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{
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#define HNS3_32_BIT_REG_RTN_DATANUM 8
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#define HNS3_32_BIT_DESC_NODATA_LEN 2
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struct hns3_cmd_desc *desc;
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uint32_t *reg_val = data;
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uint32_t *desc_data;
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int cmd_num;
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int i, k, n;
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int ret;
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if (regs_num == 0)
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return 0;
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cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
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HNS3_32_BIT_REG_RTN_DATANUM);
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desc = rte_zmalloc("hns3-32bit-regs",
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sizeof(struct hns3_cmd_desc) * cmd_num, 0);
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if (desc == NULL) {
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hns3_err(hw, "Failed to allocate %zx bytes needed to "
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"store 32bit regs",
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sizeof(struct hns3_cmd_desc) * cmd_num);
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return -ENOMEM;
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}
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hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
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ret = hns3_cmd_send(hw, desc, cmd_num);
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if (ret) {
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hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
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ret);
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rte_free(desc);
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return ret;
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}
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for (i = 0; i < cmd_num; i++) {
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if (i == 0) {
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desc_data = &desc[i].data[0];
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n = HNS3_32_BIT_REG_RTN_DATANUM -
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HNS3_32_BIT_DESC_NODATA_LEN;
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} else {
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desc_data = (uint32_t *)(&desc[i]);
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n = HNS3_32_BIT_REG_RTN_DATANUM;
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}
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for (k = 0; k < n; k++) {
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*reg_val++ = rte_le_to_cpu_32(*desc_data++);
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regs_num--;
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if (regs_num == 0)
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break;
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}
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}
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rte_free(desc);
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return 0;
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}
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static int
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hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
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{
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#define HNS3_64_BIT_REG_RTN_DATANUM 4
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#define HNS3_64_BIT_DESC_NODATA_LEN 1
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struct hns3_cmd_desc *desc;
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uint64_t *reg_val = data;
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uint64_t *desc_data;
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int cmd_num;
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int i, k, n;
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int ret;
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if (regs_num == 0)
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return 0;
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cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
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HNS3_64_BIT_REG_RTN_DATANUM);
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desc = rte_zmalloc("hns3-64bit-regs",
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sizeof(struct hns3_cmd_desc) * cmd_num, 0);
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if (desc == NULL) {
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hns3_err(hw, "Failed to allocate %zx bytes needed to "
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"store 64bit regs",
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sizeof(struct hns3_cmd_desc) * cmd_num);
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return -ENOMEM;
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}
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hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
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ret = hns3_cmd_send(hw, desc, cmd_num);
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if (ret) {
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hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
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ret);
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rte_free(desc);
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return ret;
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}
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for (i = 0; i < cmd_num; i++) {
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if (i == 0) {
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desc_data = (uint64_t *)(&desc[i].data[0]);
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n = HNS3_64_BIT_REG_RTN_DATANUM -
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HNS3_64_BIT_DESC_NODATA_LEN;
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} else {
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desc_data = (uint64_t *)(&desc[i]);
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n = HNS3_64_BIT_REG_RTN_DATANUM;
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}
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for (k = 0; k < n; k++) {
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*reg_val++ = rte_le_to_cpu_64(*desc_data++);
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regs_num--;
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if (!regs_num)
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break;
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}
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}
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rte_free(desc);
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return 0;
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}
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static void
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hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
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{
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struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
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uint32_t reg_offset;
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int separator_num;
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int reg_um;
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int i, j;
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/* fetching per-PF registers values from PF PCIe register space */
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reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
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separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
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for (i = 0; i < reg_um; i++)
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*data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
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for (i = 0; i < separator_num; i++)
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*data++ = SEPARATOR_VALUE;
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if (hns->is_vf)
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reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
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else
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reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
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separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
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for (i = 0; i < reg_um; i++)
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if (hns->is_vf)
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*data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
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else
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*data++ = hns3_read_dev(hw, common_reg_addrs[i]);
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for (i = 0; i < separator_num; i++)
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*data++ = SEPARATOR_VALUE;
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reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
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separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
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for (j = 0; j < hw->tqps_num; j++) {
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reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_REG_SIZE * j;
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for (i = 0; i < reg_um; i++)
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*data++ = hns3_read_dev(hw,
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ring_reg_addrs[i] + reg_offset);
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for (i = 0; i < separator_num; i++)
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*data++ = SEPARATOR_VALUE;
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}
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reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
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separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
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for (j = 0; j < hw->num_msi; j++) {
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reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
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for (i = 0; i < reg_um; i++)
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*data++ = hns3_read_dev(hw,
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tqp_intr_reg_addrs[i] +
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reg_offset);
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for (i = 0; i < separator_num; i++)
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*data++ = SEPARATOR_VALUE;
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}
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}
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int
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hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
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{
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struct hns3_adapter *hns = eth_dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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uint32_t regs_num_32_bit;
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uint32_t regs_num_64_bit;
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uint32_t length;
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uint32_t *data;
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int ret;
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if (regs == NULL) {
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hns3_err(hw, "the input parameter regs is NULL!");
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return -EINVAL;
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}
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ret = hns3_get_regs_length(hw, &length);
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if (ret)
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return ret;
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data = regs->data;
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if (data == NULL) {
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regs->length = length;
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regs->width = sizeof(uint32_t);
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return 0;
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}
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/* Only full register dump is supported */
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if (regs->length && regs->length != length)
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return -ENOTSUP;
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/* fetching per-PF registers values from PF PCIe register space */
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hns3_direct_access_regs(hw, data);
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if (hns->is_vf)
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return 0;
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ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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if (ret) {
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hns3_err(hw, "Get register number failed, ret = %d", ret);
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return ret;
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}
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/* fetching PF common registers values from firmware */
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ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
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if (ret) {
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hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
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return ret;
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}
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data += regs_num_32_bit;
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ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
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if (ret)
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hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
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return ret;
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}
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