2c434431f4
This commit fixes a segfault on exit by using Ctrl^C if the master lcore
was also being used as a worker core. The root cause of the issue was
that the interrupt handler was cleaning up resources such as the ethdev
and eventdev ports, and once the interrupt handler would return, that
thread would continue working as an eventdev worker, and dereference the
memory which just had free() called on it.
Fixed by moving the cleanup code from the interrupt handler to the
cleanup stage of main(), which the master thread will execute once
it has returned from its worker() functionality.
Fixes: 085edac2ca38 ("examples/eventdev_pipeline: support Tx adapter")
Cc: stable@dpdk.org
Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Tested-by: Jun W Zhou <junx.w.zhou@intel.com>
477 lines
12 KiB
C
477 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2016-2017 Intel Corporation
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*/
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#include <getopt.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <signal.h>
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#include <sched.h>
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#include "pipeline_common.h"
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struct fastpath_data *fdata;
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struct config_data cdata = {
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.num_packets = (1L << 25), /* do ~32M packets */
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.num_fids = 512,
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.queue_type = RTE_SCHED_TYPE_ATOMIC,
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.next_qid = {-1},
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.qid = {-1},
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.num_stages = 1,
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.worker_cq_depth = 16
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};
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static bool
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core_in_use(unsigned int lcore_id) {
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return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
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fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
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}
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/*
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* Parse the coremask given as argument (hexadecimal string) and fill
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* the global configuration (core role and core count) with the parsed
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* value.
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*/
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static int xdigit2val(unsigned char c)
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{
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int val;
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if (isdigit(c))
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val = c - '0';
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else if (isupper(c))
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val = c - 'A' + 10;
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else
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val = c - 'a' + 10;
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return val;
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}
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static uint64_t
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parse_coremask(const char *coremask)
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{
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int i, j, idx = 0;
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unsigned int count = 0;
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char c;
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int val;
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uint64_t mask = 0;
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const int32_t BITS_HEX = 4;
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if (coremask == NULL)
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return -1;
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/* Remove all blank characters ahead and after .
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* Remove 0x/0X if exists.
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*/
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while (isblank(*coremask))
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coremask++;
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if (coremask[0] == '0' && ((coremask[1] == 'x')
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|| (coremask[1] == 'X')))
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coremask += 2;
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i = strlen(coremask);
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while ((i > 0) && isblank(coremask[i - 1]))
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i--;
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if (i == 0)
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return -1;
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for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
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c = coremask[i];
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if (isxdigit(c) == 0) {
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/* invalid characters */
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return -1;
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}
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val = xdigit2val(c);
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for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
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if ((1 << j) & val) {
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mask |= (1UL << idx);
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count++;
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}
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}
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}
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for (; i >= 0; i--)
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if (coremask[i] != '0')
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return -1;
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if (count == 0)
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return -1;
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return mask;
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}
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static struct option long_options[] = {
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{"workers", required_argument, 0, 'w'},
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{"packets", required_argument, 0, 'n'},
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{"atomic-flows", required_argument, 0, 'f'},
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{"num_stages", required_argument, 0, 's'},
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{"rx-mask", required_argument, 0, 'r'},
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{"tx-mask", required_argument, 0, 't'},
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{"sched-mask", required_argument, 0, 'e'},
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{"cq-depth", required_argument, 0, 'c'},
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{"work-cycles", required_argument, 0, 'W'},
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{"mempool-size", required_argument, 0, 'm'},
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{"queue-priority", no_argument, 0, 'P'},
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{"parallel", no_argument, 0, 'p'},
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{"ordered", no_argument, 0, 'o'},
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{"quiet", no_argument, 0, 'q'},
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{"use-atq", no_argument, 0, 'a'},
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{"dump", no_argument, 0, 'D'},
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{0, 0, 0, 0}
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};
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static void
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usage(void)
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{
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const char *usage_str =
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" Usage: eventdev_demo [options]\n"
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" Options:\n"
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" -n, --packets=N Send N packets (default ~32M), 0 implies no limit\n"
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" -f, --atomic-flows=N Use N random flows from 1 to N (default 16)\n"
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" -s, --num_stages=N Use N atomic stages (default 1)\n"
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" -r, --rx-mask=core mask Run NIC rx on CPUs in core mask\n"
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" -w, --worker-mask=core mask Run worker on CPUs in core mask\n"
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" -t, --tx-mask=core mask Run NIC tx on CPUs in core mask\n"
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" -e --sched-mask=core mask Run scheduler on CPUs in core mask\n"
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" -c --cq-depth=N Worker CQ depth (default 16)\n"
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" -W --work-cycles=N Worker cycles (default 0)\n"
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" -P --queue-priority Enable scheduler queue prioritization\n"
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" -o, --ordered Use ordered scheduling\n"
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" -p, --parallel Use parallel scheduling\n"
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" -q, --quiet Minimize printed output\n"
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" -a, --use-atq Use all type queues\n"
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" -m, --mempool-size=N Dictate the mempool size\n"
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" -D, --dump Print detailed statistics before exit"
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"\n";
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fprintf(stderr, "%s", usage_str);
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exit(1);
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}
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static void
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parse_app_args(int argc, char **argv)
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{
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/* Parse cli options*/
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int option_index;
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int c;
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opterr = 0;
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uint64_t rx_lcore_mask = 0;
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uint64_t tx_lcore_mask = 0;
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uint64_t sched_lcore_mask = 0;
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uint64_t worker_lcore_mask = 0;
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int i;
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for (;;) {
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c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:m:paoPqDW:",
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long_options, &option_index);
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if (c == -1)
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break;
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int popcnt = 0;
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switch (c) {
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case 'n':
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cdata.num_packets = (int64_t)atol(optarg);
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if (cdata.num_packets == 0)
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cdata.num_packets = INT64_MAX;
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break;
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case 'f':
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cdata.num_fids = (unsigned int)atoi(optarg);
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break;
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case 's':
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cdata.num_stages = (unsigned int)atoi(optarg);
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break;
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case 'c':
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cdata.worker_cq_depth = (unsigned int)atoi(optarg);
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break;
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case 'W':
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cdata.worker_cycles = (unsigned int)atoi(optarg);
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break;
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case 'P':
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cdata.enable_queue_priorities = 1;
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break;
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case 'o':
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cdata.queue_type = RTE_SCHED_TYPE_ORDERED;
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break;
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case 'p':
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cdata.queue_type = RTE_SCHED_TYPE_PARALLEL;
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break;
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case 'a':
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cdata.all_type_queues = 1;
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break;
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case 'q':
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cdata.quiet = 1;
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break;
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case 'D':
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cdata.dump_dev = 1;
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break;
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case 'w':
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worker_lcore_mask = parse_coremask(optarg);
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break;
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case 'r':
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rx_lcore_mask = parse_coremask(optarg);
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popcnt = __builtin_popcountll(rx_lcore_mask);
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fdata->rx_single = (popcnt == 1);
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break;
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case 't':
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tx_lcore_mask = parse_coremask(optarg);
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popcnt = __builtin_popcountll(tx_lcore_mask);
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fdata->tx_single = (popcnt == 1);
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break;
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case 'e':
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sched_lcore_mask = parse_coremask(optarg);
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popcnt = __builtin_popcountll(sched_lcore_mask);
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fdata->sched_single = (popcnt == 1);
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break;
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case 'm':
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cdata.num_mbuf = (uint64_t)atol(optarg);
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break;
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default:
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usage();
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}
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}
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cdata.worker_lcore_mask = worker_lcore_mask;
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cdata.sched_lcore_mask = sched_lcore_mask;
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cdata.rx_lcore_mask = rx_lcore_mask;
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cdata.tx_lcore_mask = tx_lcore_mask;
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if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
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usage();
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for (i = 0; i < MAX_NUM_CORE; i++) {
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fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i));
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fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i));
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fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i));
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fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i));
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if (fdata->worker_core[i])
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cdata.num_workers++;
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if (core_in_use(i))
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cdata.active_cores++;
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}
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}
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static void
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do_capability_setup(uint8_t eventdev_id)
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{
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int ret;
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uint16_t i;
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uint8_t generic_pipeline = 0;
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uint8_t burst = 0;
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RTE_ETH_FOREACH_DEV(i) {
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uint32_t caps = 0;
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ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, i, &caps);
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if (ret)
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rte_exit(EXIT_FAILURE,
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"Invalid capability for Tx adptr port %d\n", i);
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generic_pipeline |= !(caps &
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RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT);
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}
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struct rte_event_dev_info eventdev_info;
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memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
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rte_event_dev_info_get(eventdev_id, &eventdev_info);
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burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 :
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0;
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if (generic_pipeline)
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set_worker_generic_setup_data(&fdata->cap, burst);
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else
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set_worker_tx_enq_setup_data(&fdata->cap, burst);
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}
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static void
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signal_handler(int signum)
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{
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static uint8_t once;
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uint16_t portid;
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if (fdata->done)
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rte_exit(1, "Exiting on signal %d\n", signum);
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if ((signum == SIGINT || signum == SIGTERM) && !once) {
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printf("\n\nSignal %d received, preparing to exit...\n",
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signum);
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if (cdata.dump_dev)
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rte_event_dev_dump(0, stdout);
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once = 1;
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fdata->done = 1;
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rte_smp_wmb();
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RTE_ETH_FOREACH_DEV(portid) {
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rte_event_eth_rx_adapter_stop(portid);
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rte_event_eth_tx_adapter_stop(portid);
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rte_eth_dev_stop(portid);
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}
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rte_eal_mp_wait_lcore();
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}
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if (signum == SIGTSTP)
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rte_event_dev_dump(0, stdout);
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}
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static inline uint64_t
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port_stat(int dev_id, int32_t p)
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{
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char statname[64];
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snprintf(statname, sizeof(statname), "port_%u_rx", p);
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return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
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}
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int
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main(int argc, char **argv)
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{
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struct worker_data *worker_data;
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uint16_t num_ports;
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uint16_t portid;
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int lcore_id;
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int err;
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signal(SIGINT, signal_handler);
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signal(SIGTERM, signal_handler);
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signal(SIGTSTP, signal_handler);
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err = rte_eal_init(argc, argv);
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if (err < 0)
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rte_panic("Invalid EAL arguments\n");
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argc -= err;
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argv += err;
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fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
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if (fdata == NULL)
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rte_panic("Out of memory\n");
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/* Parse cli options*/
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parse_app_args(argc, argv);
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num_ports = rte_eth_dev_count_avail();
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if (num_ports == 0)
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rte_panic("No ethernet ports found\n");
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const unsigned int cores_needed = cdata.active_cores;
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if (!cdata.quiet) {
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printf(" Config:\n");
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printf("\tports: %u\n", num_ports);
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printf("\tworkers: %u\n", cdata.num_workers);
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printf("\tpackets: %"PRIi64"\n", cdata.num_packets);
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printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
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if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED)
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printf("\tqid0 type: ordered\n");
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if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC)
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printf("\tqid0 type: atomic\n");
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printf("\tCores available: %u\n", rte_lcore_count());
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printf("\tCores used: %u\n", cores_needed);
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}
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if (rte_lcore_count() < cores_needed)
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rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
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cores_needed);
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const unsigned int ndevs = rte_event_dev_count();
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if (ndevs == 0)
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rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
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if (ndevs > 1)
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fprintf(stderr, "Warning: More than one eventdev, using idx 0");
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do_capability_setup(0);
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fdata->cap.check_opt();
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worker_data = rte_calloc(0, cdata.num_workers,
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sizeof(worker_data[0]), 0);
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if (worker_data == NULL)
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rte_panic("rte_calloc failed\n");
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int dev_id = fdata->cap.evdev_setup(worker_data);
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if (dev_id < 0)
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rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
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fdata->cap.adptr_setup(num_ports);
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/* Start the Ethernet port. */
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RTE_ETH_FOREACH_DEV(portid) {
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err = rte_eth_dev_start(portid);
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if (err < 0)
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rte_exit(EXIT_FAILURE, "Error starting ethdev %d\n",
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portid);
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}
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int worker_idx = 0;
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RTE_LCORE_FOREACH_SLAVE(lcore_id) {
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if (lcore_id >= MAX_NUM_CORE)
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break;
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if (!fdata->rx_core[lcore_id] &&
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!fdata->worker_core[lcore_id] &&
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!fdata->tx_core[lcore_id] &&
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!fdata->sched_core[lcore_id])
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continue;
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if (fdata->rx_core[lcore_id])
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printf(
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"[%s()] lcore %d executing NIC Rx\n",
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__func__, lcore_id);
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if (fdata->tx_core[lcore_id])
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printf(
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"[%s()] lcore %d executing NIC Tx\n",
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__func__, lcore_id);
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if (fdata->sched_core[lcore_id])
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printf("[%s()] lcore %d executing scheduler\n",
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__func__, lcore_id);
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if (fdata->worker_core[lcore_id])
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printf(
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"[%s()] lcore %d executing worker, using eventdev port %u\n",
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__func__, lcore_id,
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worker_data[worker_idx].port_id);
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err = rte_eal_remote_launch(fdata->cap.worker,
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&worker_data[worker_idx], lcore_id);
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if (err) {
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rte_panic("Failed to launch worker on core %d\n",
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lcore_id);
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continue;
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}
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if (fdata->worker_core[lcore_id])
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worker_idx++;
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}
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lcore_id = rte_lcore_id();
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if (core_in_use(lcore_id))
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fdata->cap.worker(&worker_data[worker_idx++]);
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rte_eal_mp_wait_lcore();
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if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
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(uint64_t)-ENOTSUP)) {
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printf("\nPort Workload distribution:\n");
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uint32_t i;
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uint64_t tot_pkts = 0;
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uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
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for (i = 0; i < cdata.num_workers; i++) {
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pkts_per_wkr[i] =
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port_stat(dev_id, worker_data[i].port_id);
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tot_pkts += pkts_per_wkr[i];
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}
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for (i = 0; i < cdata.num_workers; i++) {
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float pc = pkts_per_wkr[i] * 100 /
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((float)tot_pkts);
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printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
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i, pc, pkts_per_wkr[i]);
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}
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}
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RTE_ETH_FOREACH_DEV(portid) {
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rte_eth_dev_close(portid);
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}
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rte_event_dev_stop(0);
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rte_event_dev_close(0);
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rte_eal_cleanup();
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return 0;
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}
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