3516327e00
Add selftest as a device argument that can be enabled by suppling 'self_test=1' as a vdev parameter --vdev="event_octeontx,self_test=1" The selftest is run after vdev creation is successfully complete. Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
172 lines
5.7 KiB
C
172 lines
5.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Cavium, Inc
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*/
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#ifndef __SSOVF_EVDEV_H__
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#define __SSOVF_EVDEV_H__
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#include <rte_eventdev_pmd_vdev.h>
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#include <rte_io.h>
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#include <octeontx_mbox.h>
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#include <octeontx_ethdev.h>
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#define EVENTDEV_NAME_OCTEONTX_PMD event_octeontx
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#define SSOVF_LOG(level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, otx_logtype_ssovf, \
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"[%s] %s() " fmt "\n", \
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RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD), __func__, ## args)
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#define ssovf_log_info(fmt, ...) SSOVF_LOG(INFO, fmt, ##__VA_ARGS__)
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#define ssovf_log_dbg(fmt, ...) SSOVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
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#define ssovf_log_err(fmt, ...) SSOVF_LOG(ERR, fmt, ##__VA_ARGS__)
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#define ssovf_func_trace ssovf_log_dbg
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#define ssovf_log_selftest ssovf_log_info
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#define SSO_MAX_VHGRP (64)
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#define SSO_MAX_VHWS (32)
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/* SSO VF register offsets */
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#define SSO_VHGRP_QCTL (0x010ULL)
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#define SSO_VHGRP_INT (0x100ULL)
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#define SSO_VHGRP_INT_W1S (0x108ULL)
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#define SSO_VHGRP_INT_ENA_W1S (0x110ULL)
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#define SSO_VHGRP_INT_ENA_W1C (0x118ULL)
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#define SSO_VHGRP_INT_THR (0x140ULL)
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#define SSO_VHGRP_INT_CNT (0x180ULL)
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#define SSO_VHGRP_XAQ_CNT (0x1B0ULL)
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#define SSO_VHGRP_AQ_CNT (0x1C0ULL)
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#define SSO_VHGRP_AQ_THR (0x1E0ULL)
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/* BAR2 */
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#define SSO_VHGRP_OP_ADD_WORK0 (0x00ULL)
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#define SSO_VHGRP_OP_ADD_WORK1 (0x08ULL)
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/* SSOW VF register offsets (BAR0) */
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#define SSOW_VHWS_GRPMSK_CHGX(x) (0x080ULL | ((x) << 3))
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#define SSOW_VHWS_TAG (0x300ULL)
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#define SSOW_VHWS_WQP (0x308ULL)
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#define SSOW_VHWS_LINKS (0x310ULL)
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#define SSOW_VHWS_PENDTAG (0x340ULL)
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#define SSOW_VHWS_PENDWQP (0x348ULL)
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#define SSOW_VHWS_SWTP (0x400ULL)
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#define SSOW_VHWS_OP_ALLOC_WE (0x410ULL)
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#define SSOW_VHWS_OP_UPD_WQP_GRP0 (0x440ULL)
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#define SSOW_VHWS_OP_UPD_WQP_GRP1 (0x448ULL)
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#define SSOW_VHWS_OP_SWTAG_UNTAG (0x490ULL)
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#define SSOW_VHWS_OP_SWTAG_CLR (0x820ULL)
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#define SSOW_VHWS_OP_DESCHED (0x860ULL)
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#define SSOW_VHWS_OP_DESCHED_NOSCH (0x870ULL)
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#define SSOW_VHWS_OP_SWTAG_DESCHED (0x8C0ULL)
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#define SSOW_VHWS_OP_SWTAG_NOSCHED (0x8D0ULL)
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#define SSOW_VHWS_OP_SWTP_SET (0xC20ULL)
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#define SSOW_VHWS_OP_SWTAG_NORM (0xC80ULL)
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#define SSOW_VHWS_OP_SWTAG_FULL0 (0xCA0UL)
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#define SSOW_VHWS_OP_SWTAG_FULL1 (0xCA8ULL)
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#define SSOW_VHWS_OP_CLR_NSCHED (0x10000ULL)
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#define SSOW_VHWS_OP_GET_WORK0 (0x80000ULL)
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#define SSOW_VHWS_OP_GET_WORK1 (0x80008ULL)
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/* Mailbox message constants */
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#define SSO_COPROC 0x2
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#define SSO_GETDOMAINCFG 0x1
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#define SSO_IDENTIFY 0x2
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#define SSO_GET_DEV_INFO 0x3
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#define SSO_GET_GETWORK_WAIT 0x4
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#define SSO_SET_GETWORK_WAIT 0x5
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#define SSO_CONVERT_NS_GETWORK_ITER 0x6
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#define SSO_GRP_GET_PRIORITY 0x7
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#define SSO_GRP_SET_PRIORITY 0x8
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#define SSOVF_SELFTEST_ARG ("selftest")
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/*
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* In Cavium OcteonTX SoC, all accesses to the device registers are
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* implictly strongly ordered. So, The relaxed version of IO operation is
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* safe to use with out any IO memory barriers.
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*/
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#define ssovf_read64 rte_read64_relaxed
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#define ssovf_write64 rte_write64_relaxed
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/* ARM64 specific functions */
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#if defined(RTE_ARCH_ARM64)
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#define ssovf_load_pair(val0, val1, addr) ({ \
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asm volatile( \
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"ldp %x[x0], %x[x1], [%x[p1]]" \
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:[x0]"=r"(val0), [x1]"=r"(val1) \
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:[p1]"r"(addr) \
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); })
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#define ssovf_store_pair(val0, val1, addr) ({ \
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asm volatile( \
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"stp %x[x0], %x[x1], [%x[p1]]" \
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::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
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); })
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#else /* Un optimized functions for building on non arm64 arch */
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#define ssovf_load_pair(val0, val1, addr) \
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do { \
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val0 = rte_read64(addr); \
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val1 = rte_read64(((uint8_t *)addr) + 8); \
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} while (0)
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#define ssovf_store_pair(val0, val1, addr) \
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do { \
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rte_write64(val0, addr); \
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rte_write64(val1, (((uint8_t *)addr) + 8)); \
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} while (0)
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#endif
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struct ssovf_evdev {
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uint8_t max_event_queues;
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uint8_t max_event_ports;
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uint8_t is_timeout_deq;
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uint8_t nb_event_queues;
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uint8_t nb_event_ports;
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uint32_t min_deq_timeout_ns;
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uint32_t max_deq_timeout_ns;
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int32_t max_num_events;
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} __rte_cache_aligned;
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/* Event port aka HWS */
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struct ssows {
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uint8_t cur_tt;
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uint8_t cur_grp;
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uint8_t swtag_req;
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uint8_t *base;
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uint8_t *getwork;
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uint8_t *grps[SSO_MAX_VHGRP];
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uint8_t port;
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} __rte_cache_aligned;
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static inline struct ssovf_evdev *
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ssovf_pmd_priv(const struct rte_eventdev *eventdev)
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{
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return eventdev->data->dev_private;
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}
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extern int otx_logtype_ssovf;
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uint16_t ssows_enq(void *port, const struct rte_event *ev);
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uint16_t ssows_enq_burst(void *port,
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const struct rte_event ev[], uint16_t nb_events);
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uint16_t ssows_enq_new_burst(void *port,
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const struct rte_event ev[], uint16_t nb_events);
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uint16_t ssows_enq_fwd_burst(void *port,
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const struct rte_event ev[], uint16_t nb_events);
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uint16_t ssows_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks);
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uint16_t ssows_deq_burst(void *port, struct rte_event ev[],
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uint16_t nb_events, uint64_t timeout_ticks);
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uint16_t ssows_deq_timeout(void *port, struct rte_event *ev,
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uint64_t timeout_ticks);
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uint16_t ssows_deq_timeout_burst(void *port, struct rte_event ev[],
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uint16_t nb_events, uint64_t timeout_ticks);
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void ssows_flush_events(struct ssows *ws, uint8_t queue_id);
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void ssows_reset(struct ssows *ws);
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int test_eventdev_octeontx(void);
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#endif /* __SSOVF_EVDEV_H__ */
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