af50731085
The mbuf timestamp is moved to a dynamic field in order to allow removal of the deprecated static field. The related mbuf flag is also replaced. The registration of field and flag is done in both otx2_nix_dev_start() and otx2_nix_timesync_enable(). The dynamic offset and flag are stored in struct otx2_timesync_info to favor cache locality. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: David Marchand <david.marchand@redhat.com> Acked-by: Olivier Matz <olivier.matz@6wind.com>
451 lines
11 KiB
C
451 lines
11 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <rte_ethdev_driver.h>
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#include "otx2_ethdev.h"
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#define PTP_FREQ_ADJUST (1 << 9)
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/* Function to enable ptp config for VFs */
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void
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otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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if (otx2_nix_recalc_mtu(eth_dev))
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otx2_err("Failed to set MTU size for ptp");
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dev->scalar_ena = true;
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dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
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/* Setting up the function pointers as per new offload flags */
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otx2_eth_set_rx_function(eth_dev);
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otx2_eth_set_tx_function(eth_dev);
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}
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static uint16_t
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nix_eth_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
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{
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struct otx2_eth_rxq *rxq = queue;
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struct rte_eth_dev *eth_dev;
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RTE_SET_USED(mbufs);
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RTE_SET_USED(pkts);
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eth_dev = rxq->eth_dev;
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otx2_nix_ptp_enable_vf(eth_dev);
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return 0;
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}
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static int
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nix_read_raw_clock(struct otx2_eth_dev *dev, uint64_t *clock, uint64_t *tsc,
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uint8_t is_pmu)
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{
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struct otx2_mbox *mbox = dev->mbox;
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struct ptp_req *req;
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struct ptp_rsp *rsp;
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int rc;
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req = otx2_mbox_alloc_msg_ptp_op(mbox);
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req->op = PTP_OP_GET_CLOCK;
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req->is_pmu = is_pmu;
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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goto fail;
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if (clock)
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*clock = rsp->clk;
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if (tsc)
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*tsc = rsp->tsc;
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fail:
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return rc;
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}
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/* This function calculates two parameters "clk_freq_mult" and
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* "clk_delta" which is useful in deriving PTP HI clock from
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* timestamp counter (tsc) value.
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*/
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int
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otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev)
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{
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uint64_t ticks_base = 0, ticks = 0, tsc = 0, t_freq;
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int rc, val;
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/* Calculating the frequency at which PTP HI clock is running */
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rc = nix_read_raw_clock(dev, &ticks_base, &tsc, false);
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if (rc) {
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otx2_err("Failed to read the raw clock value: %d", rc);
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goto fail;
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}
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rte_delay_ms(100);
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rc = nix_read_raw_clock(dev, &ticks, &tsc, false);
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if (rc) {
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otx2_err("Failed to read the raw clock value: %d", rc);
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goto fail;
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}
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t_freq = (ticks - ticks_base) * 10;
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/* Calculating the freq multiplier viz the ratio between the
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* frequency at which PTP HI clock works and tsc clock runs
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*/
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dev->clk_freq_mult =
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(double)pow(10, floor(log10(t_freq))) / rte_get_timer_hz();
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val = false;
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#ifdef RTE_ARM_EAL_RDTSC_USE_PMU
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val = true;
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#endif
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rc = nix_read_raw_clock(dev, &ticks, &tsc, val);
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if (rc) {
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otx2_err("Failed to read the raw clock value: %d", rc);
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goto fail;
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}
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/* Calculating delta between PTP HI clock and tsc */
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dev->clk_delta = ((uint64_t)(ticks / dev->clk_freq_mult) - tsc);
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fail:
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return rc;
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}
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static void
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nix_start_timecounters(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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memset(&dev->systime_tc, 0, sizeof(struct rte_timecounter));
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memset(&dev->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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memset(&dev->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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dev->systime_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;
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dev->rx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;
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dev->tx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;
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}
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static int
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nix_ptp_config(struct rte_eth_dev *eth_dev, int en)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_mbox *mbox = dev->mbox;
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uint8_t rc = -EINVAL;
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if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))
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return rc;
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if (en) {
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/* Enable time stamping of sent PTP packets. */
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otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(mbox);
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rc = otx2_mbox_process(mbox);
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if (rc) {
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otx2_err("MBOX ptp tx conf enable failed: err %d", rc);
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return rc;
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}
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/* Enable time stamping of received PTP packets. */
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otx2_mbox_alloc_msg_cgx_ptp_rx_enable(mbox);
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} else {
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/* Disable time stamping of sent PTP packets. */
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otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(mbox);
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rc = otx2_mbox_process(mbox);
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if (rc) {
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otx2_err("MBOX ptp tx conf disable failed: err %d", rc);
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return rc;
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}
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/* Disable time stamping of received PTP packets. */
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otx2_mbox_alloc_msg_cgx_ptp_rx_disable(mbox);
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}
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return otx2_mbox_process(mbox);
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}
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int
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otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en)
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{
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struct otx2_eth_dev *otx2_dev = (struct otx2_eth_dev *)dev;
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struct rte_eth_dev *eth_dev;
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int i;
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if (!dev)
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return -EINVAL;
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eth_dev = otx2_dev->eth_dev;
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if (!eth_dev)
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return -EINVAL;
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otx2_dev->ptp_en = ptp_en;
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for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
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struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[i];
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rxq->mbuf_initializer =
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otx2_nix_rxq_mbuf_setup(otx2_dev,
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eth_dev->data->port_id);
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}
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if (otx2_dev_is_vf(otx2_dev) && !(otx2_dev_is_sdp(otx2_dev)) &&
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!(otx2_dev_is_lbk(otx2_dev))) {
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/* In case of VF, setting of MTU cant be done directly in this
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* function as this is running as part of MBOX request(PF->VF)
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* and MTU setting also requires MBOX message to be
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* sent(VF->PF)
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*/
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eth_dev->rx_pkt_burst = nix_eth_ptp_vf_burst;
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rte_mb();
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}
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return 0;
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}
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int
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otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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int i, rc = 0;
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/* If we are VF/SDP/LBK, ptp cannot not be enabled */
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if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev)) {
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otx2_info("PTP cannot be enabled in case of VF/SDP/LBK");
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return -EINVAL;
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}
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if (otx2_ethdev_is_ptp_en(dev)) {
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otx2_info("PTP mode is already enabled");
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return -EINVAL;
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}
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if (!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)) {
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otx2_err("Ptype offload is disabled, it should be enabled");
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return -EINVAL;
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}
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if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
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otx2_err("Both PTP and switch header enabled");
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return -EINVAL;
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}
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/* Allocating a iova address for tx tstamp */
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const struct rte_memzone *ts;
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ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",
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0, OTX2_ALIGN, OTX2_ALIGN,
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dev->node);
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if (ts == NULL) {
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otx2_err("Failed to allocate mem for tx tstamp addr");
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return -ENOMEM;
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}
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dev->tstamp.tx_tstamp_iova = ts->iova;
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dev->tstamp.tx_tstamp = ts->addr;
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rc = rte_mbuf_dyn_rx_timestamp_register(
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&dev->tstamp.tstamp_dynfield_offset,
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&dev->tstamp.rx_tstamp_dynflag);
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if (rc != 0) {
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otx2_err("Failed to register Rx timestamp field/flag");
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return -rte_errno;
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}
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/* System time should be already on by default */
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nix_start_timecounters(eth_dev);
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dev->rx_offloads |= DEV_RX_OFFLOAD_TIMESTAMP;
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dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;
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dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;
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rc = nix_ptp_config(eth_dev, 1);
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if (!rc) {
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for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
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struct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];
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otx2_nix_form_default_desc(txq);
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}
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/* Setting up the function pointers as per new offload flags */
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otx2_eth_set_rx_function(eth_dev);
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otx2_eth_set_tx_function(eth_dev);
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}
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rc = otx2_nix_recalc_mtu(eth_dev);
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if (rc)
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otx2_err("Failed to set MTU size for ptp");
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return rc;
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}
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int
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otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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int i, rc = 0;
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if (!otx2_ethdev_is_ptp_en(dev)) {
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otx2_nix_dbg("PTP mode is disabled");
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return -EINVAL;
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}
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if (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))
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return -EINVAL;
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dev->rx_offloads &= ~DEV_RX_OFFLOAD_TIMESTAMP;
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dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;
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dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;
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rc = nix_ptp_config(eth_dev, 0);
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if (!rc) {
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for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
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struct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];
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otx2_nix_form_default_desc(txq);
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}
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/* Setting up the function pointers as per new offload flags */
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otx2_eth_set_rx_function(eth_dev);
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otx2_eth_set_tx_function(eth_dev);
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}
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rc = otx2_nix_recalc_mtu(eth_dev);
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if (rc)
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otx2_err("Failed to set MTU size for ptp");
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return rc;
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}
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int
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otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
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struct timespec *timestamp,
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uint32_t __rte_unused flags)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_timesync_info *tstamp = &dev->tstamp;
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uint64_t ns;
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if (!tstamp->rx_ready)
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return -EINVAL;
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ns = rte_timecounter_update(&dev->rx_tstamp_tc, tstamp->rx_tstamp);
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*timestamp = rte_ns_to_timespec(ns);
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tstamp->rx_ready = 0;
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otx2_nix_dbg("rx timestamp: %"PRIu64" sec: %"PRIu64" nsec %"PRIu64"",
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(uint64_t)tstamp->rx_tstamp, (uint64_t)timestamp->tv_sec,
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(uint64_t)timestamp->tv_nsec);
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return 0;
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}
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int
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otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
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struct timespec *timestamp)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_timesync_info *tstamp = &dev->tstamp;
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uint64_t ns;
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if (*tstamp->tx_tstamp == 0)
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return -EINVAL;
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ns = rte_timecounter_update(&dev->tx_tstamp_tc, *tstamp->tx_tstamp);
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*timestamp = rte_ns_to_timespec(ns);
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otx2_nix_dbg("tx timestamp: %"PRIu64" sec: %"PRIu64" nsec %"PRIu64"",
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*tstamp->tx_tstamp, (uint64_t)timestamp->tv_sec,
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(uint64_t)timestamp->tv_nsec);
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*tstamp->tx_tstamp = 0;
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rte_wmb();
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return 0;
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}
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int
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otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_mbox *mbox = dev->mbox;
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struct ptp_req *req;
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struct ptp_rsp *rsp;
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int rc;
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/* Adjust the frequent to make tics increments in 10^9 tics per sec */
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if (delta < PTP_FREQ_ADJUST && delta > -PTP_FREQ_ADJUST) {
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req = otx2_mbox_alloc_msg_ptp_op(mbox);
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req->op = PTP_OP_ADJFINE;
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req->scaled_ppm = delta;
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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return rc;
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/* Since the frequency of PTP comp register is tuned, delta and
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* freq mult calculation for deriving PTP_HI from timestamp
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* counter should be done again.
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*/
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rc = otx2_nix_raw_clock_tsc_conv(dev);
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if (rc)
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otx2_err("Failed to calculate delta and freq mult");
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}
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dev->systime_tc.nsec += delta;
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dev->rx_tstamp_tc.nsec += delta;
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dev->tx_tstamp_tc.nsec += delta;
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return 0;
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}
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int
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otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
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const struct timespec *ts)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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uint64_t ns;
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ns = rte_timespec_to_ns(ts);
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/* Set the time counters to a new value. */
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dev->systime_tc.nsec = ns;
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dev->rx_tstamp_tc.nsec = ns;
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dev->tx_tstamp_tc.nsec = ns;
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return 0;
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}
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int
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otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev, struct timespec *ts)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_mbox *mbox = dev->mbox;
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struct ptp_req *req;
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struct ptp_rsp *rsp;
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uint64_t ns;
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int rc;
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req = otx2_mbox_alloc_msg_ptp_op(mbox);
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req->op = PTP_OP_GET_CLOCK;
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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return rc;
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ns = rte_timecounter_update(&dev->systime_tc, rsp->clk);
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*ts = rte_ns_to_timespec(ns);
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otx2_nix_dbg("PTP time read: %"PRIu64" .%09"PRIu64"",
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(uint64_t)ts->tv_sec, (uint64_t)ts->tv_nsec);
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return 0;
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}
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int
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otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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/* This API returns the raw PTP HI clock value. Since LFs doesn't
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* have direct access to PTP registers and it requires mbox msg
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* to AF for this value. In fastpath reading this value for every
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* packet (which involes mbox call) becomes very expensive, hence
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* we should be able to derive PTP HI clock value from tsc by
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* using freq_mult and clk_delta calculated during configure stage.
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*/
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*clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult;
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return 0;
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}
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