44f45300cb
To allow shared library builds of e.g. test-bbdev app, we need to export the configure function. Since this needs to be exported as experimental by default, we update the header file to add the experimental tag there too. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#ifndef _FPGA_LTE_FEC_H_
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#define _FPGA_LTE_FEC_H_
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#include <stdint.h>
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#include <stdbool.h>
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/**
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* @file fpga_lte_fec.h
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*
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* Interface for Intel(R) FGPA LTE FEC device configuration at the host level,
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* directly accessible by the application.
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* Configuration related to LTE Turbo coding functionality is done through
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* librte_bbdev library.
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*
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* @warning
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* @b EXPERIMENTAL: this API may change without prior notice
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**< Number of Virtual Functions FGPA 4G FEC supports */
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#define FPGA_LTE_FEC_NUM_VFS 8
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/**
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* Structure to pass FPGA 4G FEC configuration.
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*/
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struct fpga_lte_fec_conf {
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/**< 1 if PF is used for dataplane, 0 for VFs */
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bool pf_mode_en;
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/**< Number of UL queues per VF */
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uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS];
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/**< Number of DL queues per VF */
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uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS];
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/**< UL bandwidth. Needed for schedule algorithm */
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uint8_t ul_bandwidth;
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/**< DL bandwidth. Needed for schedule algorithm */
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uint8_t dl_bandwidth;
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/**< UL Load Balance */
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uint8_t ul_load_balance;
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/**< DL Load Balance */
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uint8_t dl_load_balance;
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/**< FLR timeout value */
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uint16_t flr_time_out;
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};
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/**
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* Configure Intel(R) FPGA LTE FEC device
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*
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* @param dev_name
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* The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
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* It can also be retrieved for a bbdev device from the dev_name field in the
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* rte_bbdev_info structure returned by rte_bbdev_info_get().
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* @param conf
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* Configuration to apply to FPGA 4G FEC.
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*
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* @return
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* Zero on success, negative value on failure.
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*/
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__rte_experimental
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int
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fpga_lte_fec_configure(const char *dev_name,
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const struct fpga_lte_fec_conf *conf);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FPGA_LTE_FEC_H_ */
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