3b0bc725f0
Add device arguments to lock Rx/Tx contexts. Application can either choose to lock Rx or Tx contexts by using 'lock_rx_ctx' or 'lock_tx_ctx' respectively per each port. Example: -w 0002:02:00.0,lock_rx_ctx=1 -w 0002:03:00.0,lock_tx_ctx=1 Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Reviewed-by: Andrzej Ostruszka <aostruszka@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
416 lines
10 KiB
C
416 lines
10 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include "otx2_ethdev.h"
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int
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otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev,
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uint8_t group, uint16_t *ind_tbl)
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{
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struct otx2_rss_info *rss = &dev->rss_info;
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struct otx2_mbox *mbox = dev->mbox;
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struct nix_aq_enq_req *req;
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int rc, idx;
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for (idx = 0; idx < rss->rss_size; idx++) {
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req = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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if (!req) {
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/* The shared memory buffer can be full.
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* Flush it and retry
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*/
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otx2_mbox_msg_send(mbox, 0);
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rc = otx2_mbox_wait_for_rsp(mbox, 0);
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if (rc < 0)
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return rc;
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req = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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if (!req)
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return -ENOMEM;
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}
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req->rss.rq = ind_tbl[idx];
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/* Fill AQ info */
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req->qidx = (group * rss->rss_size) + idx;
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req->ctype = NIX_AQ_CTYPE_RSS;
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req->op = NIX_AQ_INSTOP_INIT;
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if (!dev->lock_rx_ctx)
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continue;
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req = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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if (!req) {
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/* The shared memory buffer can be full.
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* Flush it and retry
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*/
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otx2_mbox_msg_send(mbox, 0);
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rc = otx2_mbox_wait_for_rsp(mbox, 0);
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if (rc < 0)
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return rc;
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req = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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if (!req)
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return -ENOMEM;
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}
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req->rss.rq = ind_tbl[idx];
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/* Fill AQ info */
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req->qidx = (group * rss->rss_size) + idx;
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req->ctype = NIX_AQ_CTYPE_RSS;
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req->op = NIX_AQ_INSTOP_LOCK;
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}
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otx2_mbox_msg_send(mbox, 0);
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rc = otx2_mbox_wait_for_rsp(mbox, 0);
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if (rc < 0)
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return rc;
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return 0;
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}
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int
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otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_rss_info *rss = &dev->rss_info;
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int rc, i, j;
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int idx = 0;
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rc = -EINVAL;
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if (reta_size != dev->rss_info.rss_size) {
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otx2_err("Size of hash lookup table configured "
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"(%d) doesn't match the number hardware can supported "
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"(%d)", reta_size, dev->rss_info.rss_size);
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goto fail;
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}
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/* Copy RETA table */
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for (i = 0; i < (dev->rss_info.rss_size / RTE_RETA_GROUP_SIZE); i++) {
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for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
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if ((reta_conf[i].mask >> j) & 0x01)
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rss->ind_tbl[idx] = reta_conf[i].reta[j];
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idx++;
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}
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}
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return otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);
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fail:
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return rc;
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}
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int
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otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct otx2_rss_info *rss = &dev->rss_info;
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int rc, i, j;
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rc = -EINVAL;
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if (reta_size != dev->rss_info.rss_size) {
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otx2_err("Size of hash lookup table configured "
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"(%d) doesn't match the number hardware can supported "
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"(%d)", reta_size, dev->rss_info.rss_size);
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goto fail;
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}
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/* Copy RETA table */
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for (i = 0; i < (dev->rss_info.rss_size / RTE_RETA_GROUP_SIZE); i++) {
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for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
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if ((reta_conf[i].mask >> j) & 0x01)
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reta_conf[i].reta[j] = rss->ind_tbl[j];
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}
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return 0;
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fail:
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return rc;
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}
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void
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otx2_nix_rss_set_key(struct otx2_eth_dev *dev, uint8_t *key,
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uint32_t key_len)
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{
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const uint8_t default_key[NIX_HASH_KEY_SIZE] = {
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,
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0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD
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};
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struct otx2_rss_info *rss = &dev->rss_info;
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uint64_t *keyptr;
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uint64_t val;
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uint32_t idx;
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if (key == NULL || key == 0) {
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keyptr = (uint64_t *)(uintptr_t)default_key;
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key_len = NIX_HASH_KEY_SIZE;
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memset(rss->key, 0, key_len);
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} else {
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memcpy(rss->key, key, key_len);
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keyptr = (uint64_t *)rss->key;
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}
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for (idx = 0; idx < (key_len >> 3); idx++) {
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val = rte_cpu_to_be_64(*keyptr);
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otx2_write64(val, dev->base + NIX_LF_RX_SECRETX(idx));
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keyptr++;
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}
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}
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static void
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rss_get_key(struct otx2_eth_dev *dev, uint8_t *key)
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{
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uint64_t *keyptr = (uint64_t *)key;
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uint64_t val;
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int idx;
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for (idx = 0; idx < (NIX_HASH_KEY_SIZE >> 3); idx++) {
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val = otx2_read64(dev->base + NIX_LF_RX_SECRETX(idx));
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*keyptr = rte_be_to_cpu_64(val);
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keyptr++;
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}
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}
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#define RSS_IPV4_ENABLE ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_FRAG_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_NONFRAG_IPV4_SCTP)
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#define RSS_IPV6_ENABLE ( \
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ETH_RSS_IPV6 | \
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ETH_RSS_FRAG_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_NONFRAG_IPV6_SCTP)
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#define RSS_IPV6_EX_ENABLE ( \
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ETH_RSS_IPV6_EX | \
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ETH_RSS_IPV6_TCP_EX | \
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ETH_RSS_IPV6_UDP_EX)
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#define RSS_MAX_LEVELS 3
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#define RSS_IPV4_INDEX 0
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#define RSS_IPV6_INDEX 1
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#define RSS_TCP_INDEX 2
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#define RSS_UDP_INDEX 3
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#define RSS_SCTP_INDEX 4
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#define RSS_DMAC_INDEX 5
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uint32_t
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otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t ethdev_rss,
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uint8_t rss_level)
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{
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uint32_t flow_key_type[RSS_MAX_LEVELS][6] = {
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{
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FLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6,
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FLOW_KEY_TYPE_TCP, FLOW_KEY_TYPE_UDP,
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FLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC
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},
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{
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FLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,
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FLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,
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FLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC
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},
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{
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FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,
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FLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,
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FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,
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FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,
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FLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,
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FLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC
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}
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};
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uint32_t flowkey_cfg = 0;
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dev->rss_info.nix_rss = ethdev_rss;
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if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
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dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B) {
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flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
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}
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if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
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flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;
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if (ethdev_rss & ETH_RSS_L3_DST_ONLY)
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flowkey_cfg |= FLOW_KEY_TYPE_L3_DST;
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if (ethdev_rss & ETH_RSS_L4_SRC_ONLY)
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flowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;
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if (ethdev_rss & ETH_RSS_L4_DST_ONLY)
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flowkey_cfg |= FLOW_KEY_TYPE_L4_DST;
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if (ethdev_rss & RSS_IPV4_ENABLE)
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flowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];
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if (ethdev_rss & RSS_IPV6_ENABLE)
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flowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];
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if (ethdev_rss & ETH_RSS_TCP)
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flowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];
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if (ethdev_rss & ETH_RSS_UDP)
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flowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];
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if (ethdev_rss & ETH_RSS_SCTP)
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flowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];
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if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
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flowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];
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if (ethdev_rss & RSS_IPV6_EX_ENABLE)
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flowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;
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if (ethdev_rss & ETH_RSS_PORT)
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flowkey_cfg |= FLOW_KEY_TYPE_PORT;
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if (ethdev_rss & ETH_RSS_NVGRE)
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flowkey_cfg |= FLOW_KEY_TYPE_NVGRE;
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if (ethdev_rss & ETH_RSS_VXLAN)
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flowkey_cfg |= FLOW_KEY_TYPE_VXLAN;
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if (ethdev_rss & ETH_RSS_GENEVE)
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flowkey_cfg |= FLOW_KEY_TYPE_GENEVE;
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if (ethdev_rss & ETH_RSS_GTPU)
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flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
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return flowkey_cfg;
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}
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int
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otx2_rss_set_hf(struct otx2_eth_dev *dev, uint32_t flowkey_cfg,
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uint8_t *alg_idx, uint8_t group, int mcam_index)
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{
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struct nix_rss_flowkey_cfg_rsp *rss_rsp;
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struct otx2_mbox *mbox = dev->mbox;
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struct nix_rss_flowkey_cfg *cfg;
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int rc;
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rc = -EINVAL;
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dev->rss_info.flowkey_cfg = flowkey_cfg;
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cfg = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(mbox);
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cfg->flowkey_cfg = flowkey_cfg;
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cfg->mcam_index = mcam_index; /* -1 indicates default group */
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cfg->group = group; /* 0 is default group */
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rc = otx2_mbox_process_msg(mbox, (void *)&rss_rsp);
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if (rc)
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return rc;
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if (alg_idx)
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*alg_idx = rss_rsp->alg_idx;
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return rc;
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}
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int
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otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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uint32_t flowkey_cfg;
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uint8_t alg_idx;
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int rc;
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rc = -EINVAL;
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if (rss_conf->rss_key && rss_conf->rss_key_len != NIX_HASH_KEY_SIZE) {
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otx2_err("Hash key size mismatch %d vs %d",
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rss_conf->rss_key_len, NIX_HASH_KEY_SIZE);
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goto fail;
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}
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if (rss_conf->rss_key)
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otx2_nix_rss_set_key(dev, rss_conf->rss_key,
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(uint32_t)rss_conf->rss_key_len);
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flowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_conf->rss_hf, 0);
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rc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,
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NIX_DEFAULT_RSS_CTX_GROUP,
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NIX_DEFAULT_RSS_MCAM_IDX);
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if (rc) {
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otx2_err("Failed to set RSS hash function rc=%d", rc);
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return rc;
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}
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dev->rss_info.alg_idx = alg_idx;
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fail:
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return rc;
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}
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int
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otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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if (rss_conf->rss_key)
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rss_get_key(dev, rss_conf->rss_key);
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rss_conf->rss_key_len = NIX_HASH_KEY_SIZE;
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rss_conf->rss_hf = dev->rss_info.nix_rss;
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return 0;
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}
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int
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otx2_nix_rss_config(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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uint32_t idx, qcnt = eth_dev->data->nb_rx_queues;
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uint32_t flowkey_cfg;
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uint64_t rss_hf;
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uint8_t alg_idx;
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int rc;
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/* Skip further configuration if selected mode is not RSS */
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if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS || !qcnt)
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return 0;
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/* Update default RSS key and cfg */
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otx2_nix_rss_set_key(dev, NULL, 0);
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/* Update default RSS RETA */
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for (idx = 0; idx < dev->rss_info.rss_size; idx++)
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dev->rss_info.ind_tbl[idx] = idx % qcnt;
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/* Init RSS table context */
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rc = otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);
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if (rc) {
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otx2_err("Failed to init RSS table rc=%d", rc);
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return rc;
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}
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rss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
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flowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_hf, 0);
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rc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,
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NIX_DEFAULT_RSS_CTX_GROUP,
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NIX_DEFAULT_RSS_MCAM_IDX);
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if (rc) {
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otx2_err("Failed to set RSS hash function rc=%d", rc);
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return rc;
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}
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dev->rss_info.alg_idx = alg_idx;
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return 0;
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}
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