3ca3dcd651
If hardware supports IEEE 1588 PTP, PTP capability will be set.
Currently, vec and sve burst is unsupported when PTP capability is set.
For sake of Rx/Tx performance, IEEE 1588 PTP is not supported in sve or
vec burst mode. When enabling IEEE 1588 PTP, Rx/Tx burst mode should be
simple or common. Rx/Tx burst mode could be set like this, for example:
-a 0000:35:00.0,rx_func_hint=common,tx_func_hint=common
This patch supports vec and sve burst when PTP is disabled. And only
support simple or common burst When PTP is enabled.
Fixes: 38b539d96e
("net/hns3: support IEEE 1588 PTP")
Cc: stable@dpdk.org
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
294 lines
6.5 KiB
C
294 lines
6.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021-2021 Hisilicon Limited.
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*/
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#include <ethdev_pci.h>
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#include <rte_io.h>
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#include <rte_time.h>
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#include "hns3_ethdev.h"
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#include "hns3_regs.h"
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#include "hns3_logs.h"
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uint64_t hns3_timestamp_rx_dynflag;
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int hns3_timestamp_dynfield_offset = -1;
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int
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hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
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struct rte_eth_conf *conf)
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{
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struct hns3_adapter *hns = dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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int ret;
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if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
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return 0;
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ret = rte_mbuf_dyn_rx_timestamp_register
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(&hns3_timestamp_dynfield_offset,
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&hns3_timestamp_rx_dynflag);
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if (ret) {
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hns3_err(hw,
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"failed to register Rx timestamp field/flag");
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return ret;
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}
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return 0;
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}
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static int
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hns3_ptp_int_en(struct hns3_hw *hw, bool en)
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{
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struct hns3_ptp_int_cmd *req;
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struct hns3_cmd_desc desc;
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int ret;
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req = (struct hns3_ptp_int_cmd *)desc.data;
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hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PTP_INT_EN, false);
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req->int_en = en ? 1 : 0;
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ret = hns3_cmd_send(hw, &desc, 1);
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if (ret)
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hns3_err(hw,
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"failed to %s ptp interrupt, ret = %d\n",
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en ? "enable" : "disable", ret);
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return ret;
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}
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int
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hns3_ptp_init(struct hns3_hw *hw)
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{
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int ret;
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if (!hns3_dev_get_support(hw, PTP))
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return 0;
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ret = hns3_ptp_int_en(hw, true);
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if (ret)
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return ret;
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/* Start PTP timer */
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hns3_write_dev(hw, HNS3_CFG_TIME_CYC_EN, 1);
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return 0;
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}
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static int
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hns3_timesync_configure(struct hns3_adapter *hns, bool en)
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{
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struct hns3_ptp_mode_cfg_cmd *req;
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struct hns3_hw *hw = &hns->hw;
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struct hns3_pf *pf = &hns->pf;
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struct hns3_cmd_desc desc;
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int val;
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int ret;
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hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PTP_MODE, false);
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req = (struct hns3_ptp_mode_cfg_cmd *)desc.data;
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val = en ? 1 : 0;
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hns3_set_bit(req->enable, HNS3_PTP_ENABLE_B, val);
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hns3_set_bit(req->enable, HNS3_PTP_TX_ENABLE_B, val);
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hns3_set_bit(req->enable, HNS3_PTP_RX_ENABLE_B, val);
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if (en) {
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hns3_set_field(req->ptp_type, HNS3_PTP_TYPE_M, HNS3_PTP_TYPE_S,
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PTP_TYPE_L2_V2_TYPE);
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hns3_set_field(req->v2_message_type_1, HNS3_PTP_MESSAGE_TYPE_M,
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HNS3_PTP_MESSAGE_TYPE_S, ALL_PTP_V2_TYPE);
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}
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ret = hns3_cmd_send(hw, &desc, 1);
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if (ret) {
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hns3_err(hw, "configure PTP time failed, en = %d, ret = %d",
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en, ret);
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return ret;
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}
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pf->ptp_enable = en;
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return 0;
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}
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int
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hns3_timesync_enable(struct rte_eth_dev *dev)
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{
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struct hns3_adapter *hns = dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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struct hns3_pf *pf = &hns->pf;
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int ret;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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if (pf->ptp_enable)
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return 0;
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hns3_warn(hw, "note: please ensure Rx/Tx burst mode is simple or common when enabling PTP!");
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rte_spinlock_lock(&hw->lock);
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ret = hns3_timesync_configure(hns, true);
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rte_spinlock_unlock(&hw->lock);
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return ret;
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}
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int
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hns3_timesync_disable(struct rte_eth_dev *dev)
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{
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struct hns3_adapter *hns = dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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struct hns3_pf *pf = &hns->pf;
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int ret;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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if (!pf->ptp_enable)
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return 0;
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rte_spinlock_lock(&hw->lock);
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ret = hns3_timesync_configure(hns, false);
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rte_spinlock_unlock(&hw->lock);
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return ret;
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}
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int
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hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp,
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uint32_t flags __rte_unused)
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{
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#define TIME_RX_STAMP_NS_MASK 0x3FFFFFFF
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struct hns3_adapter *hns = dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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struct hns3_pf *pf = &hns->pf;
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uint64_t ns, sec;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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ns = pf->rx_timestamp & TIME_RX_STAMP_NS_MASK;
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sec = upper_32_bits(pf->rx_timestamp);
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ns += sec * NSEC_PER_SEC;
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*timestamp = rte_ns_to_timespec(ns);
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return 0;
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}
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int
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hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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#define TIME_TX_STAMP_NS_MASK 0x3FFFFFFF
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#define TIME_TX_STAMP_VALID 24
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#define TIME_TX_STAMP_CNT_MASK 0x7
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struct hns3_adapter *hns = dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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uint64_t sec;
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uint64_t tmp;
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uint64_t ns;
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int ts_cnt;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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ts_cnt = hns3_read_dev(hw, HNS3_TX_1588_BACK_TSP_CNT) &
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TIME_TX_STAMP_CNT_MASK;
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if (ts_cnt == 0)
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return -EINVAL;
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ns = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_0) & TIME_TX_STAMP_NS_MASK;
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sec = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_1);
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tmp = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_2) & 0xFFFF;
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sec = (tmp << 32) | sec;
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ns += sec * NSEC_PER_SEC;
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*timestamp = rte_ns_to_timespec(ns);
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/* Clear current timestamp hardware stores */
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hns3_read_dev(hw, HNS3_TX_1588_SEQID_BACK);
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return 0;
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}
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int
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hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t ns, sec;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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sec = hns3_read_dev(hw, HNS3_CURR_TIME_OUT_L);
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sec |= (uint64_t)(hns3_read_dev(hw, HNS3_CURR_TIME_OUT_H) & 0xFFFF)
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<< 32;
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ns = hns3_read_dev(hw, HNS3_CURR_TIME_OUT_NS);
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ns += sec * NSEC_PER_SEC;
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*ts = rte_ns_to_timespec(ns);
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return 0;
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}
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int
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hns3_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
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{
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t sec = ts->tv_sec;
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uint64_t ns = ts->tv_nsec;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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/* Set the timecounters to a new value. */
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hns3_write_dev(hw, HNS3_CFG_TIME_SYNC_H, upper_32_bits(sec));
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hns3_write_dev(hw, HNS3_CFG_TIME_SYNC_M, lower_32_bits(sec));
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hns3_write_dev(hw, HNS3_CFG_TIME_SYNC_L, lower_32_bits(ns));
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hns3_write_dev(hw, HNS3_CFG_TIME_SYNC_RDY, 1);
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return 0;
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}
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int
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hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
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{
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#define TIME_SYNC_L_MASK 0x7FFFFFFF
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#define SYMBOL_BIT_OFFSET 31
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struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct timespec cur_time;
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uint64_t ns;
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if (!hns3_dev_get_support(hw, PTP))
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return -ENOTSUP;
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(void)hns3_timesync_read_time(dev, &cur_time);
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ns = rte_timespec_to_ns((const struct timespec *)&cur_time);
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cur_time = rte_ns_to_timespec(ns + delta);
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(void)hns3_timesync_write_time(dev, (const struct timespec *)&cur_time);
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return 0;
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}
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int
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hns3_restore_ptp(struct hns3_adapter *hns)
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{
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struct hns3_pf *pf = &hns->pf;
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struct hns3_hw *hw = &hns->hw;
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bool en = pf->ptp_enable;
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int ret;
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if (!hns3_dev_get_support(hw, PTP))
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return 0;
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ret = hns3_timesync_configure(hns, en);
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if (ret)
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hns3_err(hw, "restore PTP enable state(%d) failed, ret = %d",
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en, ret);
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return ret;
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}
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