53e6f86cf5
This patch updates copyright date for hns3 PMD files. Fixes:565829db8b("net/hns3: add build and doc infrastructure") Fixes:952ebacce4("net/hns3: support SVE Rx") Fixes:e31f123db0("net/hns3: support NEON Tx") Fixes:c09c7847d8("net/hns3: support traffic management") Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
154 lines
5.3 KiB
C
154 lines
5.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2021 HiSilicon Limited.
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*/
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#ifndef _HNS3_REGS_H_
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#define _HNS3_REGS_H_
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/* bar registers for cmdq */
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#define HNS3_CMDQ_TX_ADDR_L_REG 0x27000
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#define HNS3_CMDQ_TX_ADDR_H_REG 0x27004
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#define HNS3_CMDQ_TX_DEPTH_REG 0x27008
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#define HNS3_CMDQ_TX_TAIL_REG 0x27010
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#define HNS3_CMDQ_TX_HEAD_REG 0x27014
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#define HNS3_CMDQ_RX_ADDR_L_REG 0x27018
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#define HNS3_CMDQ_RX_ADDR_H_REG 0x2701c
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#define HNS3_CMDQ_RX_DEPTH_REG 0x27020
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#define HNS3_CMDQ_RX_TAIL_REG 0x27024
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#define HNS3_CMDQ_RX_HEAD_REG 0x27028
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#define HNS3_CMDQ_INTR_STS_REG 0x27104
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#define HNS3_CMDQ_INTR_EN_REG 0x27108
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#define HNS3_CMDQ_INTR_GEN_REG 0x2710C
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HNS3_VECTOR0_CMDQ_SRC_REG 0x27100
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/* Vector0 interrupt CMDQ event status register(RO) */
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#define HNS3_VECTOR0_CMDQ_STAT_REG 0x27104
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#define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
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#define HNS3_RAS_PF_OTHER_INT_STS_REG 0x20B00
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#define HNS3_RAS_REG_NFE_MASK 0xFF00
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#define HNS3_MISC_VECTOR_REG_BASE 0x20400
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#define HNS3_VECTOR0_OTER_EN_REG 0x20600
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#define HNS3_MISC_RESET_STS_REG 0x20700
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#define HNS3_GLOBAL_RESET_REG 0x20A00
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#define HNS3_FUN_RST_ING 0x20C00
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#define HNS3_GRO_EN_REG 0x28000
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#define HNS3_RPU_DROP_CNT_REG 0x28004
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#define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008
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/* Vector0 register bits for reset */
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#define HNS3_VECTOR0_FUNCRESET_INT_B 0
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#define HNS3_VECTOR0_GLOBALRESET_INT_B 5
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#define HNS3_VECTOR0_CORERESET_INT_B 6
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#define HNS3_VECTOR0_IMPRESET_INT_B 7
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/* CMDQ register bits for RX event(=MBX event) */
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#define HNS3_VECTOR0_RX_CMDQ_INT_B 1
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#define HNS3_VECTOR0_REG_MSIX_MASK 0x1FF00
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/* RST register bits for RESET event */
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#define HNS3_VECTOR0_RST_INT_B 2
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#define HNS3_VF_RST_ING 0x07008
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#define HNS3_VF_RST_ING_BIT BIT(16)
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/* bar registers for rcb */
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#define HNS3_RING_RX_BASEADDR_L_REG 0x00000
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#define HNS3_RING_RX_BASEADDR_H_REG 0x00004
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#define HNS3_RING_RX_BD_NUM_REG 0x00008
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#define HNS3_RING_RX_BD_LEN_REG 0x0000C
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#define HNS3_RING_RX_MERGE_EN_REG 0x00014
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#define HNS3_RING_RX_TAIL_REG 0x00018
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#define HNS3_RING_RX_HEAD_REG 0x0001C
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#define HNS3_RING_RX_FBDNUM_REG 0x00020
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#define HNS3_RING_RX_OFFSET_REG 0x00024
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#define HNS3_RING_RX_FBD_OFFSET_REG 0x00028
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#define HNS3_RING_RX_PKTNUM_RECORD_REG 0x0002C
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#define HNS3_RING_RX_STASH_REG 0x00030
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#define HNS3_RING_RX_BD_ERR_REG 0x00034
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#define HNS3_RING_TX_BASEADDR_L_REG 0x00040
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#define HNS3_RING_TX_BASEADDR_H_REG 0x00044
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#define HNS3_RING_TX_BD_NUM_REG 0x00048
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#define HNS3_RING_TX_PRIORITY_REG 0x0004C
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#define HNS3_RING_TX_TC_REG 0x00050
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#define HNS3_RING_TX_MERGE_EN_REG 0x00054
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#define HNS3_RING_TX_TAIL_REG 0x00058
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#define HNS3_RING_TX_HEAD_REG 0x0005C
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#define HNS3_RING_TX_FBDNUM_REG 0x00060
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#define HNS3_RING_TX_OFFSET_REG 0x00064
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#define HNS3_RING_TX_EBD_NUM_REG 0x00068
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#define HNS3_RING_TX_PKTNUM_RECORD_REG 0x0006C
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#define HNS3_RING_TX_EBD_OFFSET_REG 0x00070
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#define HNS3_RING_TX_BD_ERR_REG 0x00074
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#define HNS3_RING_EN_REG 0x00090
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#define HNS3_RING_RX_EN_REG 0x00098
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#define HNS3_RING_TX_EN_REG 0x000d4
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#define HNS3_RING_EN_B 0
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#define HNS3_TQP_REG_OFFSET 0x80000
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#define HNS3_TQP_REG_SIZE 0x200
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#define HNS3_TQP_EXT_REG_OFFSET 0x100
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#define HNS3_MIN_EXTEND_QUEUE_ID 1024
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/* bar registers for tqp interrupt */
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#define HNS3_TQP_INTR_REG_BASE 0x20000
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#define HNS3_TQP_INTR_EXT_REG_BASE 0x30000
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#define HNS3_TQP_INTR_CTRL_REG 0
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#define HNS3_TQP_INTR_GL0_REG 0x100
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#define HNS3_TQP_INTR_GL1_REG 0x200
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#define HNS3_TQP_INTR_GL2_REG 0x300
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#define HNS3_TQP_INTR_RL_REG 0x900
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#define HNS3_TQP_INTR_TX_QL_REG 0xe00
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#define HNS3_TQP_INTR_RX_QL_REG 0xf00
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#define HNS3_TQP_INTR_RL_EN_B 6
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#define HNS3_MIN_EXT_TQP_INTR_ID 64
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#define HNS3_TQP_INTR_LOW_ORDER_OFFSET 0x4
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#define HNS3_TQP_INTR_HIGH_ORDER_OFFSET 0x1000
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#define HNS3_TQP_INTR_GL_MAX 0x1FE0
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#define HNS3_TQP_INTR_GL_DEFAULT 20
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#define HNS3_TQP_INTR_GL_UNIT_1US BIT(31)
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#define HNS3_TQP_INTR_RL_MAX 0xEC
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#define HNS3_TQP_INTR_RL_ENABLE_MASK 0x40
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#define HNS3_TQP_INTR_RL_DEFAULT 0
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#define HNS3_TQP_INTR_QL_DEFAULT 0
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/* Register bit for 1588 event */
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#define HNS3_VECTOR0_1588_INT_B 0
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#define HNS3_PTP_BASE_ADDRESS 0x29000
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#define HNS3_TX_1588_SEQID_BACK (HNS3_PTP_BASE_ADDRESS + 0x0)
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#define HNS3_TX_1588_TSP_BACK_0 (HNS3_PTP_BASE_ADDRESS + 0x4)
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#define HNS3_TX_1588_TSP_BACK_1 (HNS3_PTP_BASE_ADDRESS + 0x8)
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#define HNS3_TX_1588_TSP_BACK_2 (HNS3_PTP_BASE_ADDRESS + 0xc)
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#define HNS3_TX_1588_BACK_TSP_CNT (HNS3_PTP_BASE_ADDRESS + 0x30)
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#define HNS3_CFG_TIME_SYNC_H (HNS3_PTP_BASE_ADDRESS + 0x50)
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#define HNS3_CFG_TIME_SYNC_M (HNS3_PTP_BASE_ADDRESS + 0x54)
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#define HNS3_CFG_TIME_SYNC_L (HNS3_PTP_BASE_ADDRESS + 0x58)
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#define HNS3_CFG_TIME_SYNC_RDY (HNS3_PTP_BASE_ADDRESS + 0x5c)
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#define HNS3_CFG_TIME_CYC_EN (HNS3_PTP_BASE_ADDRESS + 0x70)
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#define HNS3_CURR_TIME_OUT_H (HNS3_PTP_BASE_ADDRESS + 0x74)
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#define HNS3_CURR_TIME_OUT_L (HNS3_PTP_BASE_ADDRESS + 0x78)
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#define HNS3_CURR_TIME_OUT_NS (HNS3_PTP_BASE_ADDRESS + 0x7c)
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/* gl_usec convert to hardware count, as writing each 1 represents 2us */
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#define HNS3_GL_USEC_TO_REG(gl_usec) ((gl_usec) >> 1)
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/* rl_usec convert to hardware count, as writing each 1 represents 4us */
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#define HNS3_RL_USEC_TO_REG(rl_usec) ((rl_usec) >> 2)
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int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs);
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#endif /* _HNS3_REGS_H_ */
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