3c1199c2db
If compiled with SVE feature (e.g. "-march=armv8.2-a+sve'), the binary could not run on non-SVE platform else it will encounter illegal instruction [1]. This patch fixes it by adding 'RTE_CPUFLAG_SVE' to compile_time_cpuflags, so that rte_cpu_is_supported() will print meaningful log under above situation. [1] http://mails.dpdk.org/archives/dev/2021-May/209124.html Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
495 lines
14 KiB
Meson
495 lines
14 KiB
Meson
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017 Intel Corporation.
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# Copyright(c) 2017 Cavium, Inc
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# Copyright(c) 2021 PANTHEON.tech s.r.o.
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# common flags to all aarch64 builds, with lowest priority
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flags_common = [
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# Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
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# to determine the best threshold in code. Refer to notes in source file
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# (lib/eal/arm/include/rte_memcpy_64.h) for more info.
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['RTE_ARCH_ARM64_MEMCPY', false],
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# ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
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# ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
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# Leave below RTE_ARM64_MEMCPY_xxx options commented out,
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# unless there are strong reasons.
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# ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
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# ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
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# ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
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['RTE_SCHED_VECTOR', false],
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['RTE_ARM_USE_WFE', false],
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['RTE_ARCH_ARM64', true],
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['RTE_CACHE_LINE_SIZE', 128]
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]
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## Part numbers are specific to Arm implementers
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# implementer specific aarch64 flags have middle priority
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# (will overwrite common flags)
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# part number specific aarch64 flags have higher priority
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# (will overwrite both common and implementer specific flags)
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implementer_generic = {
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'description': 'Generic armv8',
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'flags': [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_MAX_LCORE', 256],
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['RTE_MAX_NUMA_NODES', 4]
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],
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'part_number_config': {
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'generic': {'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']}
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}
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}
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part_number_config_arm = {
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'0xd03': {'machine_args': ['-mcpu=cortex-a53']},
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'0xd04': {'machine_args': ['-mcpu=cortex-a35']},
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'0xd07': {'machine_args': ['-mcpu=cortex-a57']},
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'0xd08': {'machine_args': ['-mcpu=cortex-a72']},
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'0xd09': {'machine_args': ['-mcpu=cortex-a73']},
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'0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
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'0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
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'0xd0c': {
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'machine_args': ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
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'flags': [
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['RTE_MACHINE', '"neoverse-n1"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_MAX_MEM_MB', 1048576],
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['RTE_MAX_LCORE', 160],
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['RTE_MAX_NUMA_NODES', 2]
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]
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},
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'0xd49': {
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'machine_args': ['-march=armv8.5-a+crypto+sve2'],
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'flags': [
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['RTE_MACHINE', '"neoverse-n2"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_MAX_LCORE', 64],
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['RTE_MAX_NUMA_NODES', 1]
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]
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}
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}
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implementer_arm = {
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'description': 'Arm',
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'flags': [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_LCORE', 64],
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['RTE_MAX_NUMA_NODES', 4]
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],
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'part_number_config': part_number_config_arm
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}
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flags_part_number_thunderx = [
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['RTE_MACHINE', '"thunderx"'],
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['RTE_USE_C11_MEM_MODEL', false]
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]
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implementer_cavium = {
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'description': 'Cavium',
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'flags': [
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['RTE_MAX_VFIO_GROUPS', 128],
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['RTE_MAX_LCORE', 96],
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['RTE_MAX_NUMA_NODES', 2]
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],
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'part_number_config': {
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'0xa1': {
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'machine_args': ['-mcpu=thunderxt88'],
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'flags': flags_part_number_thunderx
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},
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'0xa2': {
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'machine_args': ['-mcpu=thunderxt81'],
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'flags': flags_part_number_thunderx
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},
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'0xa3': {
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'machine_args': ['-mcpu=thunderxt83'],
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'flags': flags_part_number_thunderx
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},
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'0xaf': {
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'machine_args': ['-march=armv8.1-a+crc+crypto', '-mcpu=thunderx2t99'],
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'flags': [
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['RTE_MACHINE', '"thunderx2"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_LCORE', 256]
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]
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},
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'0xb2': {
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'machine_args': ['-march=armv8.2-a+crc+crypto+lse', '-mcpu=octeontx2'],
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'flags': [
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['RTE_MACHINE', '"octeontx2"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_MAX_LCORE', 36],
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['RTE_MAX_NUMA_NODES', 1]
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]
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}
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}
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}
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implementer_ampere = {
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'description': 'Ampere Computing',
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'flags': [
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['RTE_MACHINE', '"emag"'],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_LCORE', 32],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'part_number_config': {
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'0x0': {'machine_args': ['-march=armv8-a+crc+crypto', '-mtune=emag']}
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}
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}
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implementer_hisilicon = {
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'description': 'HiSilicon',
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'flags': [
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 128]
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],
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'part_number_config': {
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'0xd01': {
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'machine_args': ['-march=armv8.2-a+crypto', '-mtune=tsv110'],
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'flags': [
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['RTE_MACHINE', '"Kunpeng 920"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_MAX_LCORE', 256],
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['RTE_MAX_NUMA_NODES', 8]
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]
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},
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'0xd02': {
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'machine_args': ['-march=armv8.2-a+crypto+sve'],
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'flags': [
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['RTE_MACHINE', '"Kunpeng 930"'],
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['RTE_ARM_FEATURE_ATOMICS', true],
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['RTE_MAX_LCORE', 1280],
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['RTE_MAX_NUMA_NODES', 16]
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]
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}
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}
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}
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implementer_qualcomm = {
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'description': 'Qualcomm',
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'flags': [
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['RTE_MACHINE', '"armv8a"'],
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['RTE_USE_C11_MEM_MODEL', true],
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['RTE_CACHE_LINE_SIZE', 64],
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['RTE_MAX_LCORE', 64],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'part_number_config': {
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'0xc00': {'machine_args': ['-march=armv8-a+crc']}
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}
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}
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## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
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implementers = {
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'generic': implementer_generic,
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'0x41': implementer_arm,
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'0x43': implementer_cavium,
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'0x48': implementer_hisilicon,
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'0x50': implementer_ampere,
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'0x51': implementer_qualcomm
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}
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# SoC specific aarch64 flags have the highest priority
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# (will overwrite all other flags)
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soc_generic = {
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'description': 'Generic un-optimized build for all aarch64 machines',
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'implementer': 'generic',
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'part_number': 'generic'
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}
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soc_armada = {
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'description': 'Marvell ARMADA',
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'implementer': '0x41',
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'part_number': '0xd08',
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'flags': [
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['RTE_MAX_LCORE', 16],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'numa': false
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}
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soc_bluefield = {
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'description': 'NVIDIA BlueField',
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'implementer': '0x41',
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'part_number': '0xd08',
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'flags': [
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['RTE_MAX_LCORE', 16],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'numa': false
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}
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soc_centriq2400 = {
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'description': 'Qualcomm Centriq 2400',
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'implementer': '0x51',
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'part_number': '0xc00',
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'numa': false
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}
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soc_cn10k = {
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'description' : 'Marvell OCTEON 10',
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'implementer' : '0x41',
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'flags': [
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['RTE_MAX_LCORE', 24],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'part_number': '0xd49',
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'numa': false
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}
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soc_dpaa = {
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'description': 'NXP DPAA',
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'implementer': '0x41',
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'part_number': '0xd08',
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'flags': [
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['RTE_MACHINE', '"dpaa"'],
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['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
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['RTE_MAX_LCORE', 16],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'numa': false
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}
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soc_emag = {
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'description': 'Ampere eMAG',
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'implementer': '0x50',
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'part_number': '0x0'
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}
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soc_graviton2 = {
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'description': 'AWS Graviton2',
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'implementer': '0x41',
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'part_number': '0xd0c',
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'numa': false
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}
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soc_kunpeng920 = {
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'description': 'HiSilicon Kunpeng 920',
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'implementer': '0x48',
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'part_number': '0xd01',
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'numa': true
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}
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soc_kunpeng930 = {
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'description': 'HiSilicon Kunpeng 930',
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'implementer': '0x48',
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'part_number': '0xd02',
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'numa': true
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}
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soc_n1sdp = {
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'description': 'Arm Neoverse N1SDP',
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'implementer': '0x41',
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'part_number': '0xd0c',
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'flags': [
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['RTE_MAX_LCORE', 4]
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],
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'numa': false
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}
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soc_n2 = {
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'description': 'Arm Neoverse N2',
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'implementer': '0x41',
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'part_number': '0xd49',
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'numa': false
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}
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soc_octeontx2 = {
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'description': 'Marvell OCTEON TX2',
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'implementer': '0x43',
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'part_number': '0xb2',
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'numa': false
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}
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soc_stingray = {
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'description': 'Broadcom Stingray',
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'implementer': '0x41',
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'flags': [
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['RTE_MAX_LCORE', 16],
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['RTE_MAX_NUMA_NODES', 1]
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],
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'part_number': '0xd08',
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'numa': false
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}
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soc_thunderx2 = {
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'description': 'Marvell ThunderX2 T99',
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'implementer': '0x43',
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'part_number': '0xaf'
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}
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soc_thunderxt88 = {
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'description': 'Marvell ThunderX T88',
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'implementer': '0x43',
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'part_number': '0xa1'
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}
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'''
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Start of SoCs list
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generic: Generic un-optimized build for all aarch64 machines.
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armada: Marvell ARMADA
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bluefield: NVIDIA BlueField
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centriq2400: Qualcomm Centriq 2400
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cn10k: Marvell OCTEON 10
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dpaa: NXP DPAA
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emag: Ampere eMAG
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graviton2: AWS Graviton2
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kunpeng920: HiSilicon Kunpeng 920
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kunpeng930: HiSilicon Kunpeng 930
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n1sdp: Arm Neoverse N1SDP
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n2: Arm Neoverse N2
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octeontx2: Marvell OCTEON TX2
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stingray: Broadcom Stingray
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thunderx2: Marvell ThunderX2 T99
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thunderxt88: Marvell ThunderX T88
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End of SoCs list
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'''
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# The string above is included in the documentation, keep it in sync with the
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# SoCs list below.
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socs = {
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'generic': soc_generic,
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'armada': soc_armada,
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'bluefield': soc_bluefield,
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'centriq2400': soc_centriq2400,
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'cn10k' : soc_cn10k,
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'dpaa': soc_dpaa,
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'emag': soc_emag,
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'graviton2': soc_graviton2,
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'kunpeng920': soc_kunpeng920,
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'kunpeng930': soc_kunpeng930,
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'n1sdp': soc_n1sdp,
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'n2': soc_n2,
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'octeontx2': soc_octeontx2,
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'stingray': soc_stingray,
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'thunderx2': soc_thunderx2,
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'thunderxt88': soc_thunderxt88
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}
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dpdk_conf.set('RTE_ARCH_ARM', 1)
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dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
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if dpdk_conf.get('RTE_ARCH_32')
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# armv7 build
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dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
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dpdk_conf.set('RTE_ARCH_ARMv7', 1)
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# the minimum architecture supported, armv7-a, needs the following,
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machine_args += '-mfpu=neon'
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else
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# aarch64 build
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soc = get_option('platform')
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soc_config = {}
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if not meson.is_cross_build()
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if machine == 'generic'
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# generic build
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if soc != ''
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error('Building for a particular platform is unsupported with generic build.')
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endif
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implementer_id = 'generic'
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part_number = 'generic'
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elif soc != ''
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soc_config = socs.get(soc, {'not_supported': true})
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else
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# native build
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# The script returns ['Implementer', 'Variant', 'Architecture',
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# 'Primary Part number', 'Revision']
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detect_vendor = find_program(join_paths(meson.current_source_dir(),
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'armv8_machine.py'))
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cmd = run_command(detect_vendor.path())
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if cmd.returncode() == 0
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cmd_output = cmd.stdout().to_lower().strip().split(' ')
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implementer_id = cmd_output[0]
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part_number = cmd_output[3]
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else
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error('Error when getting Arm Implementer ID and part number.')
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endif
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endif
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else
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# cross build
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soc = meson.get_cross_property('platform', '')
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if soc == ''
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error('Arm SoC must be specified in the cross file.')
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endif
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soc_config = socs.get(soc, {'not_supported': true})
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endif
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soc_flags = []
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if soc_config.has_key('not_supported')
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error('SoC @0@ not supported.'.format(soc))
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elif soc_config != {}
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implementer_id = soc_config['implementer']
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implementer_config = implementers[implementer_id]
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part_number = soc_config['part_number']
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soc_flags = soc_config.get('flags', [])
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if not soc_config.get('numa', true)
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has_libnuma = 0
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endif
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disable_drivers += ',' + soc_config.get('disable_drivers', '')
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enable_drivers += ',' + soc_config.get('enable_drivers', '')
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endif
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if implementers.has_key(implementer_id)
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implementer_config = implementers[implementer_id]
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else
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error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
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'Please add support for it or use the generic ' +
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'(-Dmachine=generic) build.')
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endif
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message('Arm implementer: ' + implementer_config['description'])
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message('Arm part number: ' + part_number)
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part_number_config = implementer_config['part_number_config']
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if part_number_config.has_key(part_number)
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# use the specified part_number machine args if found
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part_number_config = part_number_config[part_number]
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else
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# unknown part number
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error('Unsupported part number @0@ of implementer @1@. '
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.format(part_number, implementer_id) +
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'Please add support for it or use the generic ' +
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'(-Dmachine=generic) build.')
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endif
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# add/overwrite flags in the proper order
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dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
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# apply supported machine args
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machine_args = [] # Clear previous machine args
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foreach flag: part_number_config['machine_args']
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if cc.has_argument(flag)
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machine_args += flag
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endif
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endforeach
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# apply flags
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foreach flag: dpdk_flags
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if flag.length() > 0
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dpdk_conf.set(flag[0], flag[1])
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endif
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endforeach
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endif
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message('Using machine args: @0@'.format(machine_args))
|
|
|
|
if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
|
|
cc.get_define('__aarch64__', args: machine_args) != '')
|
|
compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
|
|
endif
|
|
|
|
if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
|
|
compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
|
|
endif
|
|
|
|
if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
|
|
compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
|
|
endif
|
|
|
|
if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
|
|
compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
|
|
'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
|
|
endif
|