371d3212cb
Add the make and meson based build infrastructure along with HW definition header file. This patch adds skeleton otx2_mbox.c file to make sure all header files are intact, subsequent patches add content to otx2_mbox.c This patch also updates CONFIG_RTE_MAX_VFIO_GROUPS value to 128 as the system can have up to 128 PFs/VFs. For octeontx2 meson build target, CONFIG_RTE_MAX_VFIO_GROUPS defined as 128 so no additional changes required. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_TIM_HW_H__
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#define __OTX2_TIM_HW_H__
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/* TIM */
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#define TIM_AF_CONST (0x90)
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#define TIM_PRIV_LFX_CFG(a) (0x20000 | (a) << 3)
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#define TIM_PRIV_LFX_INT_CFG(a) (0x24000 | (a) << 3)
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#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)
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#define TIM_AF_BLK_RST (0x10)
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#define TIM_AF_LF_RST (0x20)
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#define TIM_AF_BLK_RST (0x10)
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#define TIM_AF_RINGX_GMCTL(a) (0x2000 | (a) << 3)
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#define TIM_AF_RINGX_CTL0(a) (0x4000 | (a) << 3)
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#define TIM_AF_RINGX_CTL1(a) (0x6000 | (a) << 3)
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#define TIM_AF_RINGX_CTL2(a) (0x8000 | (a) << 3)
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#define TIM_AF_FLAGS_REG (0x80)
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#define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0)
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#define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47)
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#define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)
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#define TIM_AF_RINGX_CLT1_CLK_10NS (0)
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#define TIM_AF_RINGX_CLT1_CLK_GPIO (1)
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#define TIM_AF_RINGX_CLT1_CLK_GTI (2)
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#define TIM_AF_RINGX_CLT1_CLK_PTP (3)
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/* ENUMS */
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#define TIM_LF_INT_VEC_NRSPERR_INT (0x0ull)
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#define TIM_LF_INT_VEC_RAS_INT (0x1ull)
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#endif /* __OTX2_TIM_HW_H__ */
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