7b3d52989a
Firmware returns the max queues that can be allocated on the entire PF. The driver evenly distributes them across all the ports belonging to the PF. However, some ports may need more queues than others and this equal distribution scheme prevents accessing these other ports unused queues. So, remove the equal distribution scheme and allow the ports to allocate as many queues as they need. Also remove the hardcoded 64 max limit on queue allocation. Instead, use the max limit given by firmware. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
113 lines
4.2 KiB
C
113 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Chelsio Communications.
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* All rights reserved.
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*/
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#ifndef _CXGBE_H_
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#define _CXGBE_H_
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#include "base/common.h"
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#include "base/t4_regs.h"
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#define CXGBE_MIN_RING_DESC_SIZE 128 /* Min TX/RX descriptor ring size */
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#define CXGBE_MAX_RING_DESC_SIZE 4096 /* Max TX/RX descriptor ring size */
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#define CXGBE_DEFAULT_TX_DESC_SIZE 1024 /* Default TX ring size */
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#define CXGBE_DEFAULT_RX_DESC_SIZE 1024 /* Default RX ring size */
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#define CXGBE_MIN_RX_BUFSIZE RTE_ETHER_MIN_MTU /* min buf size */
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#define CXGBE_MAX_RX_PKTLEN (9000 + RTE_ETHER_HDR_LEN + \
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RTE_ETHER_CRC_LEN) /* max pkt */
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/* Max poll time is 100 * 100msec = 10 sec */
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#define CXGBE_LINK_STATUS_POLL_MS 100 /* 100ms */
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#define CXGBE_LINK_STATUS_POLL_CNT 100 /* Max number of times to poll */
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#define CXGBE_DEFAULT_RSS_KEY_LEN 40 /* 320-bits */
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#define CXGBE_RSS_HF_IPV4_MASK (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_OTHER)
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#define CXGBE_RSS_HF_IPV6_MASK (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_OTHER | \
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ETH_RSS_IPV6_EX)
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#define CXGBE_RSS_HF_TCP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_TCP | \
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ETH_RSS_IPV6_TCP_EX)
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#define CXGBE_RSS_HF_UDP_IPV6_MASK (ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_IPV6_UDP_EX)
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#define CXGBE_RSS_HF_ALL (ETH_RSS_IP | ETH_RSS_TCP | ETH_RSS_UDP)
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/* Tx/Rx Offloads supported */
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#define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_MULTI_SEGS)
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#define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP | \
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DEV_RX_OFFLOAD_IPV4_CKSUM | \
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DEV_RX_OFFLOAD_UDP_CKSUM | \
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DEV_RX_OFFLOAD_TCP_CKSUM | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | \
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DEV_RX_OFFLOAD_SCATTER | \
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DEV_RX_OFFLOAD_RSS_HASH)
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/* Devargs filtermode and filtermask representation */
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enum cxgbe_devargs_filter_mode_flags {
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CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT = (1 << 0),
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CXGBE_DEVARGS_FILTER_MODE_PF_VF = (1 << 1),
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CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC = (1 << 2),
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CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE = (1 << 3),
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CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER = (1 << 4),
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CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER = (1 << 5),
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CXGBE_DEVARGS_FILTER_MODE_IP_TOS = (1 << 6),
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CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL = (1 << 7),
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CXGBE_DEVARGS_FILTER_MODE_MAX = (1 << 8),
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};
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enum cxgbe_filter_vnic_mode {
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CXGBE_FILTER_VNIC_MODE_NONE,
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CXGBE_FILTER_VNIC_MODE_PFVF,
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CXGBE_FILTER_VNIC_MODE_OVLAN,
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};
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/* Common PF and VF devargs */
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#define CXGBE_DEVARG_CMN_KEEP_OVLAN "keep_ovlan"
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#define CXGBE_DEVARG_CMN_TX_MODE_LATENCY "tx_mode_latency"
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/* VF only devargs */
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#define CXGBE_DEVARG_VF_FORCE_LINK_UP "force_link_up"
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/* Filter Mode/Mask devargs */
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#define CXGBE_DEVARG_PF_FILTER_MODE "filtermode"
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#define CXGBE_DEVARG_PF_FILTER_MASK "filtermask"
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bool cxgbe_force_linkup(struct adapter *adap);
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int cxgbe_probe(struct adapter *adapter);
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int cxgbevf_probe(struct adapter *adapter);
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void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps);
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int cxgbe_set_link_status(struct port_info *pi, bool status);
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int cxgbe_up(struct adapter *adap);
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int cxgbe_down(struct port_info *pi);
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void cxgbe_close(struct adapter *adapter);
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void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats);
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void cxgbevf_stats_get(struct port_info *pi, struct port_stats *stats);
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void cxgbe_stats_reset(struct port_info *pi);
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int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
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unsigned int cnt, struct t4_completion *c);
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int cxgbe_link_start(struct port_info *pi);
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int cxgbe_setup_sge_fwevtq(struct adapter *adapter);
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int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter);
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int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev);
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void cxgbe_cfg_queues_free(struct adapter *adapter);
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int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev);
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int cxgbe_init_rss(struct adapter *adap);
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int cxgbe_setup_rss(struct port_info *pi);
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void cxgbe_enable_rx_queues(struct port_info *pi);
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void cxgbe_print_port_info(struct adapter *adap);
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void cxgbe_print_adapter_info(struct adapter *adap);
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void cxgbe_process_devargs(struct adapter *adap);
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void cxgbe_configure_max_ethqsets(struct adapter *adapter);
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#endif /* _CXGBE_H_ */
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