93 lines
3.0 KiB
Plaintext
93 lines
3.0 KiB
Plaintext
# BSD LICENSE
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#
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# Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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# Copyright 2016 NXP.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Freescale Semiconductor nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#include "defconfig_arm64-armv8a-linuxapp-gcc"
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# NXP (Freescale) - Soc Architecture with WRIOP and QBMAN support
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CONFIG_RTE_MACHINE="dpaa2"
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CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72"
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#
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# Compile Environment Abstraction Layer
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#
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CONFIG_RTE_MAX_LCORE=8
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CONFIG_RTE_MAX_NUMA_NODES=1
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CONFIG_RTE_CACHE_LINE_SIZE=64
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CONFIG_RTE_PKTMBUF_HEADROOM=256
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# Doesn't support NUMA
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CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
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CONFIG_RTE_LIBRTE_VHOST_NUMA=n
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#
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# Compile Support Libraries for DPAA2
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#
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CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
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CONFIG_RTE_MBUF_DEFAULT_MEMPOOL_OPS="dpaa2"
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CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=n
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#
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# Compile NXP DPAA2 FSL-MC Bus
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#
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CONFIG_RTE_LIBRTE_FSLMC_BUS=y
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#
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# Compile burst-oriented NXP DPAA2 PMD driver
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#
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CONFIG_RTE_LIBRTE_DPAA2_PMD=y
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CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n
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CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n
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CONFIG_RTE_LIBRTE_DPAA2_DEBUG_RX=n
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CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX=n
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CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX_FREE=n
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#
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# Compile NXP DPAA2 crypto sec driver for CAAM HW
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#
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CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
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CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n
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CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n
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CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n
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#
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# Number of sessions to create in the session memory pool
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# on a single DPAA2 SEC device.
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#
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CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
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#
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# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
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#
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CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y
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CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV_DEBUG=n
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