845048c522
There are two execution states on armv8 architecture, aarch64 and
aarch32. Add PLATFORM_STR for the latter and update RTE_ARCH_* flags
according to e9b9739264.
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
167 lines
4.1 KiB
C
167 lines
4.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) Cavium, Inc. 2015.
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* Copyright(c) 2015 RehiveTech. All rights reserved.
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*/
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#include "rte_cpuflags.h"
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#include <elf.h>
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#include <fcntl.h>
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#include <assert.h>
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#include <unistd.h>
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#include <string.h>
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#ifndef AT_HWCAP
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#define AT_HWCAP 16
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#endif
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#ifndef AT_HWCAP2
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#define AT_HWCAP2 26
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#endif
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#ifndef AT_PLATFORM
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#define AT_PLATFORM 15
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#endif
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enum cpu_register_t {
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REG_NONE = 0,
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REG_HWCAP,
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REG_HWCAP2,
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REG_PLATFORM,
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REG_MAX
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};
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typedef uint32_t hwcap_registers_t[REG_MAX];
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/**
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* Struct to hold a processor feature entry
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*/
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struct feature_entry {
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uint32_t reg;
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uint32_t bit;
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#define CPU_FLAG_NAME_MAX_LEN 64
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char name[CPU_FLAG_NAME_MAX_LEN];
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};
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#define FEAT_DEF(name, reg, bit) \
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[RTE_CPUFLAG_##name] = {reg, bit, #name},
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#ifdef RTE_ARCH_32
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#ifdef RTE_ARCH_ARMv7
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#define PLATFORM_STR "v7l"
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#elif defined RTE_ARCH_ARMv8_AARCH32
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#define PLATFORM_STR "v8l"
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#endif
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typedef Elf32_auxv_t _Elfx_auxv_t;
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const struct feature_entry rte_cpu_feature_table[] = {
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FEAT_DEF(SWP, REG_HWCAP, 0)
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FEAT_DEF(HALF, REG_HWCAP, 1)
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FEAT_DEF(THUMB, REG_HWCAP, 2)
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FEAT_DEF(A26BIT, REG_HWCAP, 3)
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FEAT_DEF(FAST_MULT, REG_HWCAP, 4)
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FEAT_DEF(FPA, REG_HWCAP, 5)
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FEAT_DEF(VFP, REG_HWCAP, 6)
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FEAT_DEF(EDSP, REG_HWCAP, 7)
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FEAT_DEF(JAVA, REG_HWCAP, 8)
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FEAT_DEF(IWMMXT, REG_HWCAP, 9)
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FEAT_DEF(CRUNCH, REG_HWCAP, 10)
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FEAT_DEF(THUMBEE, REG_HWCAP, 11)
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FEAT_DEF(NEON, REG_HWCAP, 12)
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FEAT_DEF(VFPv3, REG_HWCAP, 13)
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FEAT_DEF(VFPv3D16, REG_HWCAP, 14)
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FEAT_DEF(TLS, REG_HWCAP, 15)
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FEAT_DEF(VFPv4, REG_HWCAP, 16)
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FEAT_DEF(IDIVA, REG_HWCAP, 17)
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FEAT_DEF(IDIVT, REG_HWCAP, 18)
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FEAT_DEF(VFPD32, REG_HWCAP, 19)
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FEAT_DEF(LPAE, REG_HWCAP, 20)
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FEAT_DEF(EVTSTRM, REG_HWCAP, 21)
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FEAT_DEF(AES, REG_HWCAP2, 0)
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FEAT_DEF(PMULL, REG_HWCAP2, 1)
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FEAT_DEF(SHA1, REG_HWCAP2, 2)
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FEAT_DEF(SHA2, REG_HWCAP2, 3)
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FEAT_DEF(CRC32, REG_HWCAP2, 4)
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#ifdef RTE_ARCH_ARMv7
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FEAT_DEF(V7L, REG_PLATFORM, 0)
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#elif defined RTE_ARCH_ARMv8_AARCH32
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FEAT_DEF(V8L, REG_PLATFORM, 0)
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#endif
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};
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#elif defined RTE_ARCH_64
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#define PLATFORM_STR "aarch64"
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const struct feature_entry rte_cpu_feature_table[] = {
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FEAT_DEF(FP, REG_HWCAP, 0)
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FEAT_DEF(NEON, REG_HWCAP, 1)
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FEAT_DEF(EVTSTRM, REG_HWCAP, 2)
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FEAT_DEF(AES, REG_HWCAP, 3)
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FEAT_DEF(PMULL, REG_HWCAP, 4)
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FEAT_DEF(SHA1, REG_HWCAP, 5)
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FEAT_DEF(SHA2, REG_HWCAP, 6)
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FEAT_DEF(CRC32, REG_HWCAP, 7)
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FEAT_DEF(ATOMICS, REG_HWCAP, 8)
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FEAT_DEF(SVE, REG_HWCAP, 22)
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FEAT_DEF(SVE2, REG_HWCAP2, 1)
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FEAT_DEF(SVEAES, REG_HWCAP2, 2)
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FEAT_DEF(SVEPMULL, REG_HWCAP2, 3)
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FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4)
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FEAT_DEF(SVESHA3, REG_HWCAP2, 5)
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FEAT_DEF(SVESM4, REG_HWCAP2, 6)
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FEAT_DEF(FLAGM2, REG_HWCAP2, 7)
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FEAT_DEF(FRINT, REG_HWCAP2, 8)
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FEAT_DEF(SVEI8MM, REG_HWCAP2, 9)
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FEAT_DEF(SVEF32MM, REG_HWCAP2, 10)
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FEAT_DEF(SVEF64MM, REG_HWCAP2, 11)
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FEAT_DEF(SVEBF16, REG_HWCAP2, 12)
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FEAT_DEF(AARCH64, REG_PLATFORM, 0)
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};
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#endif /* RTE_ARCH */
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/*
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* Read AUXV software register and get cpu features for ARM
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*/
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static void
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rte_cpu_get_features(hwcap_registers_t out)
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{
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out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
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out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
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if (!rte_cpu_strcmp_auxval(AT_PLATFORM, PLATFORM_STR))
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out[REG_PLATFORM] = 0x0001;
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}
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/*
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* Checks if a particular flag is available on current machine.
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*/
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int
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rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
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{
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const struct feature_entry *feat;
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hwcap_registers_t regs = {0};
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if (feature >= RTE_CPUFLAG_NUMFLAGS)
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return -ENOENT;
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feat = &rte_cpu_feature_table[feature];
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if (feat->reg == REG_NONE)
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return -EFAULT;
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rte_cpu_get_features(regs);
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return (regs[feat->reg] >> feat->bit) & 1;
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}
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const char *
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rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
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{
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if (feature >= RTE_CPUFLAG_NUMFLAGS)
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return NULL;
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return rte_cpu_feature_table[feature].name;
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}
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void
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rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
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{
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memset(intrinsics, 0, sizeof(*intrinsics));
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}
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