fe55802814
Building with gcc 10.2 with SVE extension enabled got error:
{standard input}: Assembler messages:
{standard input}:4002: Error: selected processor does not support `mov z3.b,#0'
{standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7'
{standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]'
{standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7'
This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.
Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].
Fixes: 8a4f835971 ("common/octeontx2: add IO handling APIs")
Cc: stable@dpdk.org
[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_IO_ARM64_H_
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#define _OTX2_IO_ARM64_H_
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#define otx2_load_pair(val0, val1, addr) ({ \
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asm volatile( \
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"ldp %x[x0], %x[x1], [%x[p1]]" \
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:[x0]"=r"(val0), [x1]"=r"(val1) \
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:[p1]"r"(addr) \
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); })
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#define otx2_store_pair(val0, val1, addr) ({ \
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asm volatile( \
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"stp %x[x0], %x[x1], [%x[p1],#0]!" \
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::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
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); })
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#define otx2_prefetch_store_keep(ptr) ({\
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asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (ptr)); })
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#if defined(__ARM_FEATURE_SVE)
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#define __LSE_PREAMBLE " .cpu generic+lse+sve\n"
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#else
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#define __LSE_PREAMBLE " .cpu generic+lse\n"
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#endif
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static __rte_always_inline uint64_t
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otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)
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{
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uint64_t result;
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/* Atomic add with no ordering */
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asm volatile (
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__LSE_PREAMBLE
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"ldadd %x[i], %x[r], [%[b]]"
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: [r] "=r" (result), "+m" (*ptr)
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: [i] "r" (incr), [b] "r" (ptr)
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: "memory");
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return result;
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}
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static __rte_always_inline uint64_t
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otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)
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{
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uint64_t result;
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/* Atomic add with ordering */
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asm volatile (
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__LSE_PREAMBLE
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"ldadda %x[i], %x[r], [%[b]]"
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: [r] "=r" (result), "+m" (*ptr)
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: [i] "r" (incr), [b] "r" (ptr)
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: "memory");
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return result;
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}
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static __rte_always_inline uint64_t
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otx2_lmt_submit(rte_iova_t io_address)
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{
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uint64_t result;
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asm volatile (
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__LSE_PREAMBLE
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"ldeor xzr,%x[rf],[%[rs]]" :
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[rf] "=r"(result): [rs] "r"(io_address));
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return result;
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}
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static __rte_always_inline uint64_t
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otx2_lmt_submit_release(rte_iova_t io_address)
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{
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uint64_t result;
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asm volatile (
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__LSE_PREAMBLE
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"ldeorl xzr,%x[rf],[%[rs]]" :
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[rf] "=r"(result) : [rs] "r"(io_address));
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return result;
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}
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static __rte_always_inline void
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otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)
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{
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volatile const __uint128_t *src128 = (const __uint128_t *)in;
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volatile __uint128_t *dst128 = (__uint128_t *)out;
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dst128[0] = src128[0];
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dst128[1] = src128[1];
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/* lmtext receives following value:
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* 1: NIX_SUBDC_EXT needed i.e. tx vlan case
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* 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case
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*/
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if (lmtext) {
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dst128[2] = src128[2];
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if (lmtext > 1)
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dst128[3] = src128[3];
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}
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}
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static __rte_always_inline void
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otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)
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{
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volatile const __uint128_t *src128 = (const __uint128_t *)in;
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volatile __uint128_t *dst128 = (__uint128_t *)out;
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uint8_t i;
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for (i = 0; i < segdw; i++)
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dst128[i] = src128[i];
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}
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#undef __LSE_PREAMBLE
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#endif /* _OTX2_IO_ARM64_H_ */
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