4db261fc88
This patch fixes a trivial typo in mlx4 header file.
Fixes: 3d555728c9 ("net/mlx4: separate Rx/Tx definitions")
Cc: stable@dpdk.org
Signed-off-by: Rami Rosen <rami.rosen@intel.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
194 lines
6.8 KiB
C
194 lines
6.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox Technologies, Ltd
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*/
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#ifndef MLX4_RXTX_H_
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#define MLX4_RXTX_H_
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs headers do not support -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/mlx4dv.h>
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_ethdev_driver.h>
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include "mlx4.h"
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#include "mlx4_prm.h"
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/** Rx queue counters. */
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struct mlx4_rxq_stats {
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unsigned int idx; /**< Mapping index. */
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uint64_t ipackets; /**< Total of successfully received packets. */
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uint64_t ibytes; /**< Total of successfully received bytes. */
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uint64_t idropped; /**< Total of packets dropped when Rx ring full. */
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uint64_t rx_nombuf; /**< Total of Rx mbuf allocation failures. */
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};
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/** Rx queue descriptor. */
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struct rxq {
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struct priv *priv; /**< Back pointer to private data. */
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struct rte_mempool *mp; /**< Memory pool for allocations. */
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struct mlx4_mr *mr; /**< Memory region. */
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struct ibv_cq *cq; /**< Completion queue. */
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struct ibv_wq *wq; /**< Work queue. */
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struct ibv_comp_channel *channel; /**< Rx completion channel. */
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uint16_t rq_ci; /**< Saved RQ consumer index. */
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uint16_t port_id; /**< Port ID for incoming packets. */
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uint16_t sges_n; /**< Number of segments per packet (log2 value). */
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uint16_t elts_n; /**< Mbuf queue size (log2 value). */
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struct rte_mbuf *(*elts)[]; /**< Rx elements. */
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volatile struct mlx4_wqe_data_seg (*wqes)[]; /**< HW queue entries. */
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volatile uint32_t *rq_db; /**< RQ doorbell record. */
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uint32_t csum:1; /**< Enable checksum offloading. */
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uint32_t csum_l2tun:1; /**< Same for L2 tunnels. */
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uint32_t l2tun_offload:1; /**< L2 tunnel offload is enabled. */
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struct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */
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struct mlx4_rxq_stats stats; /**< Rx queue counters. */
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unsigned int socket; /**< CPU socket ID for allocations. */
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uint32_t usecnt; /**< Number of users relying on queue resources. */
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uint8_t data[]; /**< Remaining queue resources. */
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};
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/** Shared flow target for Rx queues. */
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struct mlx4_rss {
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LIST_ENTRY(mlx4_rss) next; /**< Next entry in list. */
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struct priv *priv; /**< Back pointer to private data. */
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uint32_t refcnt; /**< Reference count for this object. */
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uint32_t usecnt; /**< Number of users relying on @p qp and @p ind. */
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struct ibv_qp *qp; /**< Queue pair. */
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struct ibv_rwq_ind_table *ind; /**< Indirection table. */
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uint64_t fields; /**< Fields for RSS processing (Verbs format). */
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uint8_t key[MLX4_RSS_HASH_KEY_SIZE]; /**< Hash key to use. */
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uint16_t queues; /**< Number of target queues. */
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uint16_t queue_id[]; /**< Target queues. */
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};
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/** Tx element. */
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struct txq_elt {
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struct rte_mbuf *buf; /**< Buffer. */
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union {
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volatile struct mlx4_wqe_ctrl_seg *wqe; /**< SQ WQE. */
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volatile uint32_t *eocb; /**< End of completion burst. */
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};
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};
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/** Tx queue counters. */
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struct mlx4_txq_stats {
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unsigned int idx; /**< Mapping index. */
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uint64_t opackets; /**< Total of successfully sent packets. */
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uint64_t obytes; /**< Total of successfully sent bytes. */
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uint64_t odropped; /**< Total of packets not sent when Tx ring full. */
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};
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/** Tx queue descriptor. */
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struct txq {
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struct mlx4_sq msq; /**< Info for directly manipulating the SQ. */
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struct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */
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unsigned int elts_head; /**< Current index in (*elts)[]. */
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unsigned int elts_tail; /**< First element awaiting completion. */
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int elts_comp_cd; /**< Countdown for next completion. */
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unsigned int elts_comp_cd_init; /**< Initial value for countdown. */
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unsigned int elts_n; /**< (*elts)[] length. */
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struct txq_elt (*elts)[]; /**< Tx elements. */
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struct mlx4_txq_stats stats; /**< Tx queue counters. */
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uint32_t max_inline; /**< Max inline send size. */
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uint32_t csum:1; /**< Enable checksum offloading. */
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uint32_t csum_l2tun:1; /**< Same for L2 tunnels. */
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uint32_t lb:1; /**< Whether packets should be looped back by eSwitch. */
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uint8_t *bounce_buf;
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/**< Memory used for storing the first DWORD of data TXBBs. */
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struct {
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const struct rte_mempool *mp; /**< Cached memory pool. */
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struct mlx4_mr *mr; /**< Memory region (for mp). */
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uint32_t lkey; /**< mr->lkey copy. */
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} mp2mr[MLX4_PMD_TX_MP_CACHE]; /**< MP to MR translation table. */
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struct priv *priv; /**< Back pointer to private data. */
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unsigned int socket; /**< CPU socket ID for allocations. */
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struct ibv_cq *cq; /**< Completion queue. */
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struct ibv_qp *qp; /**< Queue pair. */
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uint8_t data[]; /**< Remaining queue resources. */
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};
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/* mlx4_rxq.c */
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uint8_t mlx4_rss_hash_key_default[MLX4_RSS_HASH_KEY_SIZE];
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int mlx4_rss_init(struct priv *priv);
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void mlx4_rss_deinit(struct priv *priv);
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struct mlx4_rss *mlx4_rss_get(struct priv *priv, uint64_t fields,
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uint8_t key[MLX4_RSS_HASH_KEY_SIZE],
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uint16_t queues, const uint16_t queue_id[]);
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void mlx4_rss_put(struct mlx4_rss *rss);
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int mlx4_rss_attach(struct mlx4_rss *rss);
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void mlx4_rss_detach(struct mlx4_rss *rss);
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int mlx4_rxq_attach(struct rxq *rxq);
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void mlx4_rxq_detach(struct rxq *rxq);
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uint64_t mlx4_get_rx_port_offloads(struct priv *priv);
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uint64_t mlx4_get_rx_queue_offloads(struct priv *priv);
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int mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
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uint16_t desc, unsigned int socket,
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const struct rte_eth_rxconf *conf,
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struct rte_mempool *mp);
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void mlx4_rx_queue_release(void *dpdk_rxq);
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/* mlx4_rxtx.c */
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uint16_t mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
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uint16_t pkts_n);
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uint16_t mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
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uint16_t pkts_n);
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uint16_t mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts,
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uint16_t pkts_n);
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uint16_t mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts,
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uint16_t pkts_n);
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/* mlx4_txq.c */
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uint64_t mlx4_get_tx_port_offloads(struct priv *priv);
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int mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
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uint16_t desc, unsigned int socket,
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const struct rte_eth_txconf *conf);
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void mlx4_tx_queue_release(void *dpdk_txq);
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/**
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* Get memory region (MR) <-> memory pool (MP) association from txq->mp2mr[].
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* Call mlx4_txq_add_mr() if MP is not registered yet.
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*
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* @param txq
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* Pointer to Tx queue structure.
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* @param[in] mp
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* Memory pool for which a memory region lkey must be returned.
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*
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* @return
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* mr->lkey on success, (uint32_t)-1 on failure.
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*/
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static inline uint32_t
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mlx4_txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
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{
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unsigned int i;
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for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
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if (unlikely(txq->mp2mr[i].mp == NULL)) {
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/* Unknown MP, add a new MR for it. */
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break;
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}
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if (txq->mp2mr[i].mp == mp) {
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/* MP found MP. */
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return txq->mp2mr[i].lkey;
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}
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}
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return mlx4_txq_add_mr(txq, mp, i);
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}
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#endif /* MLX4_RXTX_H_ */
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