50370662b7
Normally when starting/stopping the device the queue should be started and stopped. Support them both in this patch. Below ops are added, dev_configure dev_start dev_stop dev_close dev_reset rx_queue_start rx_queue_stop tx_queue_start tx_queue_stop rx_queue_setup rx_queue_release tx_queue_setup tx_queue_release Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Signed-off-by: Qiming Yang <qiming.yang@intel.com> Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com> Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
138 lines
4.9 KiB
C
138 lines
4.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _ICE_RXTX_H_
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#define _ICE_RXTX_H_
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#include "ice_ethdev.h"
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#define ICE_ALIGN_RING_DESC 32
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#define ICE_MIN_RING_DESC 64
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#define ICE_MAX_RING_DESC 4096
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#define ICE_DMA_MEM_ALIGN 4096
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#define ICE_RING_BASE_ALIGN 128
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#define ICE_RX_MAX_BURST 32
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#define ICE_TX_MAX_BURST 32
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#define ICE_CHK_Q_ENA_COUNT 100
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#define ICE_CHK_Q_ENA_INTERVAL_US 100
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#ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
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#define ice_rx_desc ice_16byte_rx_desc
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#else
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#define ice_rx_desc ice_32byte_rx_desc
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#endif
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#define ICE_SUPPORT_CHAIN_NUM 5
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struct ice_rx_entry {
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struct rte_mbuf *mbuf;
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};
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struct ice_rx_queue {
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struct rte_mempool *mp; /* mbuf pool to populate RX ring */
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volatile union ice_rx_desc *rx_ring;/* RX ring virtual address */
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uint64_t rx_ring_phys_addr; /* RX ring DMA address */
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struct ice_rx_entry *sw_ring; /* address of RX soft ring */
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uint16_t nb_rx_desc; /* number of RX descriptors */
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uint16_t rx_free_thresh; /* max free RX desc to hold */
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uint16_t rx_tail; /* current value of tail */
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uint16_t nb_rx_hold; /* number of held free RX desc */
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struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
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struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
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#ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
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uint16_t rx_nb_avail; /**< number of staged packets ready */
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uint16_t rx_next_avail; /**< index of next staged packets */
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uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
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struct rte_mbuf fake_mbuf; /**< dummy mbuf */
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struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
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#endif
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uint8_t port_id; /* device port ID */
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uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
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uint16_t queue_id; /* RX queue index */
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uint16_t reg_idx; /* RX queue register index */
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uint8_t drop_en; /* if not 0, set register bit */
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volatile uint8_t *qrx_tail; /* register address of tail */
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struct ice_vsi *vsi; /* the VSI this queue belongs to */
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uint16_t rx_buf_len; /* The packet buffer size */
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uint16_t rx_hdr_len; /* The header buffer size */
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uint16_t max_pkt_len; /* Maximum packet length */
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bool q_set; /* indicate if rx queue has been configured */
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bool rx_deferred_start; /* don't start this queue in dev start */
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};
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struct ice_tx_entry {
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struct rte_mbuf *mbuf;
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uint16_t next_id;
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uint16_t last_id;
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};
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struct ice_tx_queue {
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uint16_t nb_tx_desc; /* number of TX descriptors */
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uint64_t tx_ring_phys_addr; /* TX ring DMA address */
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volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
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struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
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uint16_t tx_tail; /* current value of tail register */
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volatile uint8_t *qtx_tail; /* register address of tail */
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uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
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/* index to last TX descriptor to have been cleaned */
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uint16_t last_desc_cleaned;
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/* Total number of TX descriptors ready to be allocated. */
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uint16_t nb_tx_free;
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/* Start freeing TX buffers if there are less free descriptors than
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* this value.
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*/
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uint16_t tx_free_thresh;
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/* Number of TX descriptors to use before RS bit is set. */
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uint16_t tx_rs_thresh;
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uint8_t pthresh; /**< Prefetch threshold register. */
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uint8_t hthresh; /**< Host threshold register. */
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uint8_t wthresh; /**< Write-back threshold reg. */
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uint8_t port_id; /* Device port identifier. */
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uint16_t queue_id; /* TX queue index. */
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uint32_t q_teid; /* TX schedule node id. */
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uint16_t reg_idx;
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uint64_t offloads;
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struct ice_vsi *vsi; /* the VSI this queue belongs to */
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uint16_t tx_next_dd;
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uint16_t tx_next_rs;
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bool tx_deferred_start; /* don't start this queue in dev start */
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bool q_set; /* indicate if tx queue has been configured */
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};
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/* Offload features */
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union ice_tx_offload {
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uint64_t data;
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struct {
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uint64_t l2_len:7; /* L2 (MAC) Header Length. */
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uint64_t l3_len:9; /* L3 (IP) Header Length. */
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uint64_t l4_len:8; /* L4 Header Length. */
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uint64_t tso_segsz:16; /* TCP TSO segment size */
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uint64_t outer_l2_len:8; /* outer L2 Header Length */
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uint64_t outer_l3_len:16; /* outer L3 Header Length */
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};
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};
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int ice_rx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int ice_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void ice_rx_queue_release(void *rxq);
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void ice_tx_queue_release(void *txq);
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void ice_clear_queues(struct rte_eth_dev *dev);
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void ice_free_queues(struct rte_eth_dev *dev);
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#endif /* _ICE_RXTX_H_ */
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