d6c31f2065
For enabling outbound inline IPsec, a CPT queue needs to be tied to a NIX PF_FUNC. Distribute CPT queues fairly among all available otx2 eth ports. For inbound, one CPT LF will be assigned and initialized by kernel. Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com> Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Archana Muniganti <marchana@marvell.com> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
33 lines
927 B
C
33 lines
927 B
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_CRYPTODEV_MBOX_H_
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#define _OTX2_CRYPTODEV_MBOX_H_
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#include <rte_cryptodev.h>
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#include "otx2_cryptodev_hw_access.h"
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int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
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uint16_t *nb_queues);
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int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues);
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int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);
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int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);
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int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
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uint64_t *val);
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int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
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uint64_t val);
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int otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev,
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struct otx2_cpt_qp *qp, uint16_t port_id);
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int otx2_cpt_inline_init(const struct rte_cryptodev *dev);
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#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
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