51fafb89a9
There was no direct association between the rxq's VNIC and the
vnic_info[].
Explicitly associate the two in bnxt_mq_rx_configure().
Fixes: 0a256e4a54 ("net/bnxt: fix Rx ring count limitation")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
349 lines
9.3 KiB
C
349 lines
9.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Broadcom
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* All rights reserved.
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*/
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#ifndef _BNXT_H_
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#define _BNXT_H_
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#include <inttypes.h>
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#include <stdbool.h>
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#include <sys/queue.h>
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#include <rte_pci.h>
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#include <rte_bus_pci.h>
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#include <rte_ethdev_driver.h>
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#include <rte_memory.h>
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#include <rte_lcore.h>
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#include <rte_spinlock.h>
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#include <rte_time.h>
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#include "bnxt_cpr.h"
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#define BNXT_MAX_MTU 9500
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#define VLAN_TAG_SIZE 4
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#define BNXT_VF_RSV_NUM_RSS_CTX 1
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#define BNXT_VF_RSV_NUM_L2_CTX 4
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/* TODO: For now, do not support VMDq/RFS on VFs. */
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#define BNXT_VF_RSV_NUM_VNIC 1
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#define BNXT_MAX_LED 4
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#define BNXT_NUM_VLANS 2
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#define BNXT_MIN_RING_DESC 16
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#define BNXT_MAX_TX_RING_DESC 4096
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#define BNXT_MAX_RX_RING_DESC 8192
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#define BNXT_DB_SIZE 0x80
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#define BNXT_INT_LAT_TMR_MIN 75
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#define BNXT_INT_LAT_TMR_MAX 150
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#define BNXT_NUM_CMPL_AGGR_INT 36
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#define BNXT_CMPL_AGGR_DMA_TMR 37
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#define BNXT_NUM_CMPL_DMA_AGGR 36
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#define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
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#define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
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struct bnxt_led_info {
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uint8_t led_id;
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uint8_t led_type;
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uint8_t led_group_id;
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uint8_t unused;
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uint16_t led_state_caps;
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#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
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rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
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uint16_t led_color_caps;
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};
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struct bnxt_led_cfg {
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uint8_t led_id;
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uint8_t led_state;
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uint8_t led_color;
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uint8_t unused;
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uint16_t led_blink_on;
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uint16_t led_blink_off;
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uint8_t led_group_id;
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uint8_t rsvd;
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};
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#define BNXT_LED_DFLT_ENA \
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(HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
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HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
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HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
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HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
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HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
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#define BNXT_LED_DFLT_ENA_SHIFT 6
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#define BNXT_LED_DFLT_ENABLES(x) \
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rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
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enum bnxt_hw_context {
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HW_CONTEXT_NONE = 0,
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HW_CONTEXT_IS_RSS = 1,
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HW_CONTEXT_IS_COS = 2,
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HW_CONTEXT_IS_LB = 3,
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};
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struct bnxt_vlan_table_entry {
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uint16_t tpid;
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uint16_t vid;
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} __attribute__((packed));
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struct bnxt_vlan_antispoof_table_entry {
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uint16_t tpid;
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uint16_t vid;
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uint16_t mask;
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} __attribute__((packed));
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struct bnxt_child_vf_info {
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void *req_buf;
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struct bnxt_vlan_table_entry *vlan_table;
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struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
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STAILQ_HEAD(, bnxt_filter_info) filter;
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uint32_t func_cfg_flags;
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uint32_t l2_rx_mask;
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uint16_t fid;
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uint16_t max_tx_rate;
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uint16_t dflt_vlan;
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uint16_t vlan_count;
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uint8_t mac_spoof_en;
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uint8_t vlan_spoof_en;
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bool random_mac;
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bool persist_stats;
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};
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struct bnxt_pf_info {
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#define BNXT_FIRST_PF_FID 1
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#define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
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#define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
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#define BNXT_FIRST_VF_FID 128
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#define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
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#define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
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uint16_t port_id;
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uint16_t first_vf_id;
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uint16_t active_vfs;
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uint16_t max_vfs;
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uint16_t total_vfs; /* Total VFs possible.
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* Not necessarily enabled.
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*/
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uint32_t func_cfg_flags;
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void *vf_req_buf;
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rte_iova_t vf_req_buf_dma_addr;
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uint32_t vf_req_fwd[8];
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uint16_t total_vnics;
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struct bnxt_child_vf_info *vf_info;
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#define BNXT_EVB_MODE_NONE 0
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#define BNXT_EVB_MODE_VEB 1
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#define BNXT_EVB_MODE_VEPA 2
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uint8_t evb_mode;
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};
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/* Max wait time is 10 * 100ms = 1s */
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#define BNXT_LINK_WAIT_CNT 10
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#define BNXT_LINK_WAIT_INTERVAL 100
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struct bnxt_link_info {
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uint32_t phy_flags;
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uint8_t mac_type;
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uint8_t phy_link_status;
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uint8_t loop_back;
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uint8_t link_up;
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uint8_t duplex;
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uint8_t pause;
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uint8_t force_pause;
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uint8_t auto_pause;
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uint8_t auto_mode;
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#define PHY_VER_LEN 3
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uint8_t phy_ver[PHY_VER_LEN];
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uint16_t link_speed;
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uint16_t support_speeds;
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uint16_t auto_link_speed;
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uint16_t force_link_speed;
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uint16_t auto_link_speed_mask;
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uint32_t preemphasis;
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uint8_t phy_type;
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uint8_t media_type;
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};
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#define BNXT_COS_QUEUE_COUNT 8
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struct bnxt_cos_queue_info {
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uint8_t id;
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uint8_t profile;
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};
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struct rte_flow {
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STAILQ_ENTRY(rte_flow) next;
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struct bnxt_filter_info *filter;
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struct bnxt_vnic_info *vnic;
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};
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struct bnxt_ptp_cfg {
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#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
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#define BNXT_GRCPF_REG_SYNC_TIME 0x480
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#define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
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struct rte_timecounter tc;
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struct rte_timecounter tx_tstamp_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct bnxt *bp;
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#define BNXT_MAX_TX_TS 1
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uint16_t rxctl;
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#define BNXT_PTP_MSG_SYNC (1 << 0)
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#define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
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#define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
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#define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
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#define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
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#define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
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#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
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#define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
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#define BNXT_PTP_MSG_SIGNALING (1 << 12)
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#define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
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#define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
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BNXT_PTP_MSG_DELAY_REQ | \
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BNXT_PTP_MSG_PDELAY_REQ | \
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BNXT_PTP_MSG_PDELAY_RESP)
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uint8_t tx_tstamp_en:1;
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int rx_filter;
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#define BNXT_PTP_RX_TS_L 0
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#define BNXT_PTP_RX_TS_H 1
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#define BNXT_PTP_RX_SEQ 2
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#define BNXT_PTP_RX_FIFO 3
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#define BNXT_PTP_RX_FIFO_PENDING 0x1
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#define BNXT_PTP_RX_FIFO_ADV 4
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#define BNXT_PTP_RX_REGS 5
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#define BNXT_PTP_TX_TS_L 0
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#define BNXT_PTP_TX_TS_H 1
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#define BNXT_PTP_TX_SEQ 2
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#define BNXT_PTP_TX_FIFO 3
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#define BNXT_PTP_TX_FIFO_EMPTY 0x2
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#define BNXT_PTP_TX_REGS 4
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uint32_t rx_regs[BNXT_PTP_RX_REGS];
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uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
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uint32_t tx_regs[BNXT_PTP_TX_REGS];
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uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
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};
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struct bnxt_coal {
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uint16_t num_cmpl_aggr_int;
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uint16_t num_cmpl_dma_aggr;
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uint16_t num_cmpl_dma_aggr_during_int;
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uint16_t int_lat_tmr_max;
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uint16_t int_lat_tmr_min;
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uint16_t cmpl_aggr_dma_tmr;
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uint16_t cmpl_aggr_dma_tmr_during_int;
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};
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#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
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struct bnxt {
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void *bar0;
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struct rte_eth_dev *eth_dev;
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struct rte_eth_rss_conf rss_conf;
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struct rte_pci_device *pdev;
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void *doorbell_base;
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uint32_t flags;
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#define BNXT_FLAG_REGISTERED (1 << 0)
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#define BNXT_FLAG_VF (1 << 1)
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#define BNXT_FLAG_PORT_STATS (1 << 2)
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#define BNXT_FLAG_JUMBO (1 << 3)
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#define BNXT_FLAG_SHORT_CMD (1 << 4)
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#define BNXT_FLAG_UPDATE_HASH (1 << 5)
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#define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
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#define BNXT_FLAG_MULTI_HOST (1 << 7)
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#define BNXT_FLAG_NEW_RM (1 << 30)
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#define BNXT_FLAG_INIT_DONE (1 << 31)
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#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
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#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
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#define BNXT_NPAR(bp) ((bp)->port_partition_type)
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#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
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#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
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unsigned int rx_nr_rings;
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unsigned int rx_cp_nr_rings;
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struct bnxt_rx_queue **rx_queues;
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const void *rx_mem_zone;
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struct rx_port_stats *hw_rx_port_stats;
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rte_iova_t hw_rx_port_stats_map;
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unsigned int tx_nr_rings;
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unsigned int tx_cp_nr_rings;
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struct bnxt_tx_queue **tx_queues;
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const void *tx_mem_zone;
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struct tx_port_stats *hw_tx_port_stats;
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rte_iova_t hw_tx_port_stats_map;
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/* Default completion ring */
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struct bnxt_cp_ring_info *def_cp_ring;
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uint32_t max_ring_grps;
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struct bnxt_ring_grp_info *grp_info;
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unsigned int nr_vnics;
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struct bnxt_vnic_info *vnic_info;
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STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
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struct bnxt_filter_info *filter_info;
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STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
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struct bnxt_irq *irq_tbl;
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#define MAX_NUM_MAC_ADDR 32
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint16_t hwrm_cmd_seq;
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void *hwrm_cmd_resp_addr;
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rte_iova_t hwrm_cmd_resp_dma_addr;
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void *hwrm_short_cmd_req_addr;
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rte_iova_t hwrm_short_cmd_req_dma_addr;
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rte_spinlock_t hwrm_lock;
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uint16_t max_req_len;
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uint16_t max_resp_len;
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struct bnxt_link_info link_info;
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struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
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uint8_t tx_cosq_id;
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uint16_t fw_fid;
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uint8_t dflt_mac_addr[ETHER_ADDR_LEN];
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uint16_t max_rsscos_ctx;
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uint16_t max_cp_rings;
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uint16_t max_tx_rings;
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uint16_t max_rx_rings;
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uint16_t max_l2_ctx;
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uint16_t max_vnics;
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uint16_t max_stat_ctx;
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uint16_t vlan;
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struct bnxt_pf_info pf;
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uint8_t port_partition_type;
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uint8_t dev_stopped;
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uint8_t vxlan_port_cnt;
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uint8_t geneve_port_cnt;
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uint16_t vxlan_port;
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uint16_t geneve_port;
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uint16_t vxlan_fw_dst_port_id;
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uint16_t geneve_fw_dst_port_id;
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uint32_t fw_ver;
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uint32_t hwrm_spec_code;
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struct bnxt_led_info leds[BNXT_MAX_LED];
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uint8_t num_leds;
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struct bnxt_ptp_cfg *ptp_cfg;
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uint16_t vf_resv_strategy;
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};
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int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
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int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
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bool is_bnxt_supported(struct rte_eth_dev *dev);
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bool bnxt_stratus_device(struct bnxt *bp);
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extern const struct rte_flow_ops bnxt_flow_ops;
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extern int bnxt_logtype_driver;
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#define PMD_DRV_LOG_RAW(level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
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__func__, ## args)
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#define PMD_DRV_LOG(level, fmt, args...) \
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PMD_DRV_LOG_RAW(level, fmt, ## args)
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#endif
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