39 lines
1.2 KiB
Plaintext
39 lines
1.2 KiB
Plaintext
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2017 Cavium, Inc
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#
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#include "common_linuxapp"
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CONFIG_RTE_MACHINE="armv8a"
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CONFIG_RTE_ARCH="arm64"
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CONFIG_RTE_ARCH_ARM64=y
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CONFIG_RTE_ARCH_64=y
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CONFIG_RTE_FORCE_INTRINSICS=y
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# Maximum available cache line size in arm64 implementations.
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# Setting to maximum available cache line size in generic config
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# to address minimum DMA alignment across all arm64 implementations.
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CONFIG_RTE_CACHE_LINE_SIZE=128
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# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
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# to determine the best threshold in code. Refer to notes in source file
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# (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
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CONFIG_RTE_ARCH_ARM64_MEMCPY=n
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#CONFIG_RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD=2048
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#CONFIG_RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD=512
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# Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
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# strong reasons.
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#CONFIG_RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK=n
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#CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF
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#CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n
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CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
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CONFIG_RTE_LIBRTE_FM10K_PMD=n
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CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
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CONFIG_RTE_LIBRTE_AVP_PMD=n
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CONFIG_RTE_SCHED_VECTOR=n
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