26aeabe079
Add support for dequeue, dequeue_burst, ... DLB does not currently support interrupts, but instead uses umonitor/umwait if supported by the processor. This allows the software to monitor and wait on writes to a cache-line. DLB supports normal and sparse cq mode. In normal mode the hardware will pack 4 QEs into each cache line. In sparse cq mode, the hardware will only populate one QE per cache line. Software must be aware of the cq mode, and take the appropriate actions, based on the mode. Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com> Reviewed-by: Gage Eads <gage.eads@intel.com> |
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| .. | ||
| dlb2.rst | ||
| dlb.rst | ||
| dpaa2.rst | ||
| dpaa.rst | ||
| dsw.rst | ||
| index.rst | ||
| octeontx2.rst | ||
| octeontx.rst | ||
| opdl.rst | ||
| sw.rst | ||