52c8620022
Use the new API to wait in low power state instead of continuous polling to save CPU cycles and power. Signed-off-by: Gavin Hu <gavin.hu@arm.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
677 lines
20 KiB
C
677 lines
20 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2016 Cavium, Inc
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*/
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#include <unistd.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <rte_atomic.h>
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#include <rte_branch_prediction.h>
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#include <rte_byteorder.h>
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#include <rte_common.h>
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#include <rte_cycles.h>
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#include <rte_errno.h>
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#include <rte_ethdev_driver.h>
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#include <rte_ether.h>
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#include <rte_log.h>
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#include <rte_mbuf.h>
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#include <rte_prefetch.h>
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#include "base/nicvf_plat.h"
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#include "nicvf_ethdev.h"
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#include "nicvf_rxtx.h"
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#include "nicvf_logs.h"
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static inline void __hot
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fill_sq_desc_header(union sq_entry_t *entry, struct rte_mbuf *pkt)
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{
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/* Local variable sqe to avoid read from sq desc memory*/
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union sq_entry_t sqe;
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uint64_t ol_flags;
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/* Fill SQ header descriptor */
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sqe.buff[0] = 0;
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sqe.hdr.subdesc_type = SQ_DESC_TYPE_HEADER;
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/* Number of sub-descriptors following this one */
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sqe.hdr.subdesc_cnt = pkt->nb_segs;
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sqe.hdr.tot_len = pkt->pkt_len;
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ol_flags = pkt->ol_flags & NICVF_TX_OFFLOAD_MASK;
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if (unlikely(ol_flags)) {
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/* L4 cksum */
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uint64_t l4_flags = ol_flags & PKT_TX_L4_MASK;
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if (l4_flags == PKT_TX_TCP_CKSUM)
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sqe.hdr.csum_l4 = SEND_L4_CSUM_TCP;
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else if (l4_flags == PKT_TX_UDP_CKSUM)
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sqe.hdr.csum_l4 = SEND_L4_CSUM_UDP;
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else
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sqe.hdr.csum_l4 = SEND_L4_CSUM_DISABLE;
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sqe.hdr.l3_offset = pkt->l2_len;
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sqe.hdr.l4_offset = pkt->l3_len + pkt->l2_len;
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/* L3 cksum */
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if (ol_flags & PKT_TX_IP_CKSUM)
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sqe.hdr.csum_l3 = 1;
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}
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entry->buff[0] = sqe.buff[0];
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}
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static inline void __hot
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fill_sq_desc_header_zero_w1(union sq_entry_t *entry,
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struct rte_mbuf *pkt)
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{
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fill_sq_desc_header(entry, pkt);
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entry->buff[1] = 0ULL;
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}
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void __hot
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nicvf_single_pool_free_xmited_buffers(struct nicvf_txq *sq)
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{
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int j = 0;
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uint32_t curr_head;
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uint32_t head = sq->head;
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struct rte_mbuf **txbuffs = sq->txbuffs;
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void *obj_p[NICVF_MAX_TX_FREE_THRESH] __rte_cache_aligned;
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curr_head = nicvf_addr_read(sq->sq_head) >> 4;
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while (head != curr_head) {
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if (txbuffs[head])
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obj_p[j++] = txbuffs[head];
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head = (head + 1) & sq->qlen_mask;
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}
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rte_mempool_put_bulk(sq->pool, obj_p, j);
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sq->head = curr_head;
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sq->xmit_bufs -= j;
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NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
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}
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void __hot
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nicvf_multi_pool_free_xmited_buffers(struct nicvf_txq *sq)
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{
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uint32_t n = 0;
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uint32_t curr_head;
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uint32_t head = sq->head;
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struct rte_mbuf **txbuffs = sq->txbuffs;
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curr_head = nicvf_addr_read(sq->sq_head) >> 4;
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while (head != curr_head) {
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if (txbuffs[head]) {
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rte_pktmbuf_free_seg(txbuffs[head]);
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n++;
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}
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head = (head + 1) & sq->qlen_mask;
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}
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sq->head = curr_head;
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sq->xmit_bufs -= n;
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NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
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}
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static inline uint32_t __hot
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nicvf_free_tx_desc(struct nicvf_txq *sq)
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{
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return ((sq->head - sq->tail - 1) & sq->qlen_mask);
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}
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/* Send Header + Packet */
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#define TX_DESC_PER_PKT 2
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static inline uint32_t __hot
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nicvf_free_xmitted_buffers(struct nicvf_txq *sq, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts)
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{
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uint32_t free_desc = nicvf_free_tx_desc(sq);
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if (free_desc < nb_pkts * TX_DESC_PER_PKT ||
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sq->xmit_bufs > sq->tx_free_thresh) {
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if (unlikely(sq->pool == NULL))
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sq->pool = tx_pkts[0]->pool;
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sq->pool_free(sq);
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/* Freed now, let see the number of free descs again */
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free_desc = nicvf_free_tx_desc(sq);
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}
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return free_desc;
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}
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uint16_t __hot
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nicvf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
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{
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int i;
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uint32_t free_desc;
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uint32_t tail;
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struct nicvf_txq *sq = tx_queue;
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union sq_entry_t *desc_ptr = sq->desc;
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struct rte_mbuf **txbuffs = sq->txbuffs;
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struct rte_mbuf *pkt;
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uint32_t qlen_mask = sq->qlen_mask;
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tail = sq->tail;
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free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
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for (i = 0; i < nb_pkts && (int)free_desc >= TX_DESC_PER_PKT; i++) {
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pkt = tx_pkts[i];
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txbuffs[tail] = NULL;
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fill_sq_desc_header(desc_ptr + tail, pkt);
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tail = (tail + 1) & qlen_mask;
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txbuffs[tail] = pkt;
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fill_sq_desc_gather(desc_ptr + tail, pkt);
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tail = (tail + 1) & qlen_mask;
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free_desc -= TX_DESC_PER_PKT;
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}
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if (likely(i)) {
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sq->tail = tail;
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sq->xmit_bufs += i;
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rte_wmb();
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/* Inform HW to xmit the packets */
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nicvf_addr_write(sq->sq_door, i * TX_DESC_PER_PKT);
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}
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return i;
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}
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uint16_t __hot
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nicvf_xmit_pkts_multiseg(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts)
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{
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int i, k;
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uint32_t used_desc, next_used_desc, used_bufs, free_desc, tail;
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struct nicvf_txq *sq = tx_queue;
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union sq_entry_t *desc_ptr = sq->desc;
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struct rte_mbuf **txbuffs = sq->txbuffs;
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struct rte_mbuf *pkt, *seg;
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uint32_t qlen_mask = sq->qlen_mask;
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uint16_t nb_segs;
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tail = sq->tail;
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used_desc = 0;
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used_bufs = 0;
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free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
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for (i = 0; i < nb_pkts; i++) {
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pkt = tx_pkts[i];
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nb_segs = pkt->nb_segs;
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next_used_desc = used_desc + nb_segs + 1;
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if (next_used_desc > free_desc)
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break;
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used_desc = next_used_desc;
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used_bufs += nb_segs;
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txbuffs[tail] = NULL;
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fill_sq_desc_header_zero_w1(desc_ptr + tail, pkt);
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tail = (tail + 1) & qlen_mask;
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txbuffs[tail] = pkt;
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fill_sq_desc_gather(desc_ptr + tail, pkt);
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tail = (tail + 1) & qlen_mask;
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seg = pkt->next;
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for (k = 1; k < nb_segs; k++) {
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txbuffs[tail] = seg;
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fill_sq_desc_gather(desc_ptr + tail, seg);
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tail = (tail + 1) & qlen_mask;
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seg = seg->next;
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}
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}
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if (likely(used_desc)) {
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sq->tail = tail;
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sq->xmit_bufs += used_bufs;
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rte_wmb();
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/* Inform HW to xmit the packets */
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nicvf_addr_write(sq->sq_door, used_desc);
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}
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return i;
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}
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static const uint32_t ptype_table[16][16] __rte_cache_aligned = {
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[L3_NONE][L4_NONE] = RTE_PTYPE_UNKNOWN,
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[L3_NONE][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
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[L3_NONE][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
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[L3_NONE][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
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[L3_NONE][L4_TCP] = RTE_PTYPE_L4_TCP,
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[L3_NONE][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
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[L3_NONE][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
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[L3_NONE][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
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[L3_NONE][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
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[L3_NONE][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
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[L3_NONE][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
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[L3_IPV4][L4_NONE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
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[L3_IPV4][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV4,
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[L3_IPV4][L4_IPFRAG] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_FRAG,
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[L3_IPV4][L4_IPCOMP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
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[L3_IPV4][L4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
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[L3_IPV4][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
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[L3_IPV4][L4_GRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GRE,
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[L3_IPV4][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
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[L3_IPV4][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GENEVE,
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[L3_IPV4][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_VXLAN,
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[L3_IPV4][L4_NVGRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_NVGRE,
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[L3_IPV4_OPT][L4_NONE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
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[L3_IPV4_OPT][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4_EXT |
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RTE_PTYPE_L3_IPV4,
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[L3_IPV4_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_FRAG,
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[L3_IPV4_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
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[L3_IPV4_OPT][L4_TCP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
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[L3_IPV4_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
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[L3_IPV4_OPT][L4_GRE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_GRE,
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[L3_IPV4_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
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[L3_IPV4_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4_EXT |
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RTE_PTYPE_TUNNEL_GENEVE,
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[L3_IPV4_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4_EXT |
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RTE_PTYPE_TUNNEL_VXLAN,
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[L3_IPV4_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV4_EXT |
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RTE_PTYPE_TUNNEL_NVGRE,
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[L3_IPV6][L4_NONE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
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[L3_IPV6][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L3_IPV4,
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[L3_IPV6][L4_IPFRAG] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_FRAG,
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[L3_IPV6][L4_IPCOMP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
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[L3_IPV6][L4_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
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[L3_IPV6][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
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[L3_IPV6][L4_GRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GRE,
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[L3_IPV6][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
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[L3_IPV6][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GENEVE,
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[L3_IPV6][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_VXLAN,
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[L3_IPV6][L4_NVGRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_NVGRE,
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[L3_IPV6_OPT][L4_NONE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
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[L3_IPV6_OPT][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6_EXT |
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RTE_PTYPE_L3_IPV4,
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[L3_IPV6_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_FRAG,
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[L3_IPV6_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
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[L3_IPV6_OPT][L4_TCP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
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[L3_IPV6_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
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[L3_IPV6_OPT][L4_GRE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_TUNNEL_GRE,
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[L3_IPV6_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
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[L3_IPV6_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6_EXT |
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RTE_PTYPE_TUNNEL_GENEVE,
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[L3_IPV6_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6_EXT |
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RTE_PTYPE_TUNNEL_VXLAN,
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[L3_IPV6_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV6_EXT |
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RTE_PTYPE_TUNNEL_NVGRE,
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[L3_ET_STOP][L4_NONE] = RTE_PTYPE_UNKNOWN,
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[L3_ET_STOP][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
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[L3_ET_STOP][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
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[L3_ET_STOP][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
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[L3_ET_STOP][L4_TCP] = RTE_PTYPE_L4_TCP,
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[L3_ET_STOP][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
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[L3_ET_STOP][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
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[L3_ET_STOP][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
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[L3_ET_STOP][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
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[L3_ET_STOP][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
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[L3_ET_STOP][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
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[L3_OTHER][L4_NONE] = RTE_PTYPE_UNKNOWN,
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[L3_OTHER][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
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[L3_OTHER][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
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[L3_OTHER][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
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[L3_OTHER][L4_TCP] = RTE_PTYPE_L4_TCP,
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[L3_OTHER][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
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[L3_OTHER][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
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[L3_OTHER][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
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[L3_OTHER][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
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[L3_OTHER][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
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[L3_OTHER][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
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};
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static inline uint32_t __hot
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nicvf_rx_classify_pkt(cqe_rx_word0_t cqe_rx_w0)
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{
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return ptype_table[cqe_rx_w0.l3_type][cqe_rx_w0.l4_type];
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}
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static inline uint64_t __hot
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nicvf_set_olflags(const cqe_rx_word0_t cqe_rx_w0)
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{
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static const uint64_t flag_table[3] __rte_cache_aligned = {
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PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
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PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_UNKNOWN,
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PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
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};
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const uint8_t idx = (cqe_rx_w0.err_opcode == CQE_RX_ERR_L4_CHK) << 1 |
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(cqe_rx_w0.err_opcode == CQE_RX_ERR_IP_CHK);
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return flag_table[idx];
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}
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static inline int __hot
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nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill)
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{
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int i;
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uint32_t ltail, next_tail;
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|
struct nicvf_rbdr *rbdr = rxq->shared_rbdr;
|
|
uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
|
|
struct rbdr_entry_t *desc = rbdr->desc;
|
|
uint32_t qlen_mask = rbdr->qlen_mask;
|
|
uintptr_t door = rbdr->rbdr_door;
|
|
void *obj_p[NICVF_MAX_RX_FREE_THRESH] __rte_cache_aligned;
|
|
|
|
if (unlikely(rte_mempool_get_bulk(rxq->pool, obj_p, to_fill) < 0)) {
|
|
rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
|
|
to_fill;
|
|
return 0;
|
|
}
|
|
|
|
NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
|
|
(nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
|
|
|
|
next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
|
|
__ATOMIC_ACQUIRE);
|
|
ltail = next_tail;
|
|
for (i = 0; i < to_fill; i++) {
|
|
struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);
|
|
|
|
entry->full_addr = nicvf_mbuff_virt2phy((uintptr_t)obj_p[i],
|
|
mbuf_phys_off);
|
|
ltail++;
|
|
}
|
|
|
|
rte_wait_until_equal_32(&rbdr->tail, next_tail, __ATOMIC_RELAXED);
|
|
|
|
__atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
|
|
nicvf_addr_write(door, to_fill);
|
|
return to_fill;
|
|
}
|
|
|
|
static inline int32_t __hot
|
|
nicvf_rx_pkts_to_process(struct nicvf_rxq *rxq, uint16_t nb_pkts,
|
|
int32_t available_space)
|
|
{
|
|
if (unlikely(available_space < nb_pkts))
|
|
rxq->available_space = nicvf_addr_read(rxq->cq_status)
|
|
& NICVF_CQ_CQE_COUNT_MASK;
|
|
|
|
return RTE_MIN(nb_pkts, available_space);
|
|
}
|
|
|
|
static inline void __hot
|
|
nicvf_rx_offload(cqe_rx_word0_t cqe_rx_w0, cqe_rx_word2_t cqe_rx_w2,
|
|
struct rte_mbuf *pkt)
|
|
{
|
|
if (likely(cqe_rx_w0.rss_alg)) {
|
|
pkt->hash.rss = cqe_rx_w2.rss_tag;
|
|
pkt->ol_flags |= PKT_RX_RSS_HASH;
|
|
|
|
}
|
|
}
|
|
|
|
static __rte_always_inline uint16_t
|
|
nicvf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
|
|
const uint32_t flag)
|
|
{
|
|
uint32_t i, to_process;
|
|
struct cqe_rx_t *cqe_rx;
|
|
struct rte_mbuf *pkt;
|
|
cqe_rx_word0_t cqe_rx_w0;
|
|
cqe_rx_word1_t cqe_rx_w1;
|
|
cqe_rx_word2_t cqe_rx_w2;
|
|
cqe_rx_word3_t cqe_rx_w3;
|
|
struct nicvf_rxq *rxq = rx_queue;
|
|
union cq_entry_t *desc = rxq->desc;
|
|
const uint64_t cqe_mask = rxq->qlen_mask;
|
|
uint64_t rb0_ptr, mbuf_phys_off = rxq->mbuf_phys_off;
|
|
const uint64_t mbuf_init = rxq->mbuf_initializer.value;
|
|
uint32_t cqe_head = rxq->head & cqe_mask;
|
|
int32_t available_space = rxq->available_space;
|
|
const uint8_t rbptr_offset = rxq->rbptr_offset;
|
|
|
|
to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
|
|
|
|
for (i = 0; i < to_process; i++) {
|
|
rte_prefetch_non_temporal(&desc[cqe_head + 2]);
|
|
cqe_rx = (struct cqe_rx_t *)&desc[cqe_head];
|
|
NICVF_RX_ASSERT(((struct cq_entry_type_t *)cqe_rx)->cqe_type
|
|
== CQE_TYPE_RX);
|
|
|
|
NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
|
|
NICVF_LOAD_PAIR(cqe_rx_w2.u64, cqe_rx_w3.u64, &cqe_rx->word2);
|
|
rb0_ptr = *((uint64_t *)cqe_rx + rbptr_offset);
|
|
pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
|
|
(rb0_ptr - cqe_rx_w1.align_pad, mbuf_phys_off);
|
|
|
|
if (flag & NICVF_RX_OFFLOAD_NONE)
|
|
pkt->ol_flags = 0;
|
|
if (flag & NICVF_RX_OFFLOAD_CKSUM)
|
|
pkt->ol_flags = nicvf_set_olflags(cqe_rx_w0);
|
|
if (flag & NICVF_RX_OFFLOAD_VLAN_STRIP) {
|
|
if (unlikely(cqe_rx_w0.vlan_stripped)) {
|
|
pkt->ol_flags |= PKT_RX_VLAN
|
|
| PKT_RX_VLAN_STRIPPED;
|
|
pkt->vlan_tci =
|
|
rte_cpu_to_be_16(cqe_rx_w2.vlan_tci);
|
|
}
|
|
}
|
|
pkt->data_len = cqe_rx_w3.rb0_sz;
|
|
pkt->pkt_len = cqe_rx_w3.rb0_sz;
|
|
pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
|
|
nicvf_mbuff_init_update(pkt, mbuf_init, cqe_rx_w1.align_pad);
|
|
nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
|
|
rx_pkts[i] = pkt;
|
|
cqe_head = (cqe_head + 1) & cqe_mask;
|
|
nicvf_prefetch_store_keep(pkt);
|
|
}
|
|
|
|
if (likely(to_process)) {
|
|
rxq->available_space -= to_process;
|
|
rxq->head = cqe_head;
|
|
nicvf_addr_write(rxq->cq_door, to_process);
|
|
rxq->recv_buffers += to_process;
|
|
}
|
|
if (rxq->recv_buffers > rxq->rx_free_thresh) {
|
|
rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
|
|
NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
|
|
}
|
|
|
|
return to_process;
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_no_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_NONE);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_cksum(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_CKSUM);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_vlan_strip(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_NONE | NICVF_RX_OFFLOAD_VLAN_STRIP);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_cksum_vlan_strip(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_CKSUM | NICVF_RX_OFFLOAD_VLAN_STRIP);
|
|
}
|
|
|
|
static __rte_always_inline uint16_t __hot
|
|
nicvf_process_cq_mseg_entry(struct cqe_rx_t *cqe_rx,
|
|
uint64_t mbuf_phys_off,
|
|
struct rte_mbuf **rx_pkt, uint8_t rbptr_offset,
|
|
uint64_t mbuf_init, const uint32_t flag)
|
|
{
|
|
struct rte_mbuf *pkt, *seg, *prev;
|
|
cqe_rx_word0_t cqe_rx_w0;
|
|
cqe_rx_word1_t cqe_rx_w1;
|
|
cqe_rx_word2_t cqe_rx_w2;
|
|
uint16_t *rb_sz, nb_segs, seg_idx;
|
|
uint64_t *rb_ptr;
|
|
|
|
NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
|
|
NICVF_RX_ASSERT(cqe_rx_w0.cqe_type == CQE_TYPE_RX);
|
|
cqe_rx_w2 = cqe_rx->word2;
|
|
rb_sz = &cqe_rx->word3.rb0_sz;
|
|
rb_ptr = (uint64_t *)cqe_rx + rbptr_offset;
|
|
nb_segs = cqe_rx_w0.rb_cnt;
|
|
pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
|
|
(rb_ptr[0] - cqe_rx_w1.align_pad, mbuf_phys_off);
|
|
|
|
pkt->pkt_len = cqe_rx_w1.pkt_len;
|
|
pkt->data_len = rb_sz[nicvf_frag_num(0)];
|
|
nicvf_mbuff_init_mseg_update(
|
|
pkt, mbuf_init, cqe_rx_w1.align_pad, nb_segs);
|
|
pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
|
|
if (flag & NICVF_RX_OFFLOAD_NONE)
|
|
pkt->ol_flags = 0;
|
|
if (flag & NICVF_RX_OFFLOAD_CKSUM)
|
|
pkt->ol_flags = nicvf_set_olflags(cqe_rx_w0);
|
|
if (flag & NICVF_RX_OFFLOAD_VLAN_STRIP) {
|
|
if (unlikely(cqe_rx_w0.vlan_stripped)) {
|
|
pkt->ol_flags |= PKT_RX_VLAN
|
|
| PKT_RX_VLAN_STRIPPED;
|
|
pkt->vlan_tci = rte_cpu_to_be_16(cqe_rx_w2.vlan_tci);
|
|
}
|
|
}
|
|
nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
|
|
|
|
*rx_pkt = pkt;
|
|
prev = pkt;
|
|
for (seg_idx = 1; seg_idx < nb_segs; seg_idx++) {
|
|
seg = (struct rte_mbuf *)nicvf_mbuff_phy2virt
|
|
(rb_ptr[seg_idx], mbuf_phys_off);
|
|
|
|
prev->next = seg;
|
|
seg->data_len = rb_sz[nicvf_frag_num(seg_idx)];
|
|
nicvf_mbuff_init_update(seg, mbuf_init, 0);
|
|
|
|
prev = seg;
|
|
}
|
|
prev->next = NULL;
|
|
return nb_segs;
|
|
}
|
|
|
|
static __rte_always_inline uint16_t __hot
|
|
nicvf_recv_pkts_multiseg(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts, const uint32_t flag)
|
|
{
|
|
union cq_entry_t *cq_entry;
|
|
struct cqe_rx_t *cqe_rx;
|
|
struct nicvf_rxq *rxq = rx_queue;
|
|
union cq_entry_t *desc = rxq->desc;
|
|
const uint64_t cqe_mask = rxq->qlen_mask;
|
|
uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
|
|
uint32_t i, to_process, cqe_head, buffers_consumed = 0;
|
|
int32_t available_space = rxq->available_space;
|
|
uint16_t nb_segs;
|
|
const uint64_t mbuf_init = rxq->mbuf_initializer.value;
|
|
const uint8_t rbptr_offset = rxq->rbptr_offset;
|
|
|
|
cqe_head = rxq->head & cqe_mask;
|
|
to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
|
|
|
|
for (i = 0; i < to_process; i++) {
|
|
rte_prefetch_non_temporal(&desc[cqe_head + 2]);
|
|
cq_entry = &desc[cqe_head];
|
|
cqe_rx = (struct cqe_rx_t *)cq_entry;
|
|
nb_segs = nicvf_process_cq_mseg_entry(cqe_rx, mbuf_phys_off,
|
|
rx_pkts + i, rbptr_offset, mbuf_init, flag);
|
|
buffers_consumed += nb_segs;
|
|
cqe_head = (cqe_head + 1) & cqe_mask;
|
|
nicvf_prefetch_store_keep(rx_pkts[i]);
|
|
}
|
|
|
|
if (likely(to_process)) {
|
|
rxq->available_space -= to_process;
|
|
rxq->head = cqe_head;
|
|
nicvf_addr_write(rxq->cq_door, to_process);
|
|
rxq->recv_buffers += buffers_consumed;
|
|
}
|
|
if (rxq->recv_buffers > rxq->rx_free_thresh) {
|
|
rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
|
|
NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
|
|
}
|
|
|
|
return to_process;
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_multiseg_no_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_NONE);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_multiseg_cksum(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_CKSUM);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_multiseg_vlan_strip(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_NONE | NICVF_RX_OFFLOAD_VLAN_STRIP);
|
|
}
|
|
|
|
uint16_t __hot
|
|
nicvf_recv_pkts_multiseg_cksum_vlan_strip(void *rx_queue,
|
|
struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
|
|
{
|
|
return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
|
|
NICVF_RX_OFFLOAD_CKSUM | NICVF_RX_OFFLOAD_VLAN_STRIP);
|
|
}
|
|
|
|
uint32_t
|
|
nicvf_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
|
|
{
|
|
struct nicvf_rxq *rxq;
|
|
|
|
rxq = dev->data->rx_queues[queue_idx];
|
|
return nicvf_addr_read(rxq->cq_status) & NICVF_CQ_CQE_COUNT_MASK;
|
|
}
|
|
|
|
uint32_t
|
|
nicvf_dev_rbdr_refill(struct rte_eth_dev *dev, uint16_t queue_idx)
|
|
{
|
|
struct nicvf_rxq *rxq;
|
|
uint32_t to_process;
|
|
uint32_t rx_free;
|
|
|
|
rxq = dev->data->rx_queues[queue_idx];
|
|
to_process = rxq->recv_buffers;
|
|
while (rxq->recv_buffers > 0) {
|
|
rx_free = RTE_MIN(rxq->recv_buffers, NICVF_MAX_RX_FREE_THRESH);
|
|
rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rx_free);
|
|
}
|
|
|
|
assert(rxq->recv_buffers == 0);
|
|
return to_process;
|
|
}
|