6bd7fbd03c
As described in series starting at [1], it adds option to set
metadata value as match pattern when creating a new flow rule.
This patch adds metadata support in mlx5 driver, in two parts:
- Add the validation and setting of metadata value in matcher,
when creating a new flow rule.
- Add the passing of metadata value from mbuf to wqe when
indicated by ol_flag, in different burst functions.
[1] "ethdev: support metadata as flow rule criteria"
http://mails.dpdk.org/archives/dev/2018-September/113269.html
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
121 lines
4.1 KiB
C
121 lines
4.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_RXTX_VEC_H_
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#define RTE_PMD_MLX5_RXTX_VEC_H_
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#include <rte_common.h>
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#include <rte_mbuf.h>
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#include "mlx5_autoconf.h"
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#include "mlx5_prm.h"
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/* HW checksum offload capabilities of vectorized Tx. */
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#define MLX5_VEC_TX_CKSUM_OFFLOAD_CAP \
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(DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
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/* HW offload capabilities of vectorized Tx. */
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#define MLX5_VEC_TX_OFFLOAD_CAP \
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(MLX5_VEC_TX_CKSUM_OFFLOAD_CAP | \
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DEV_TX_OFFLOAD_MATCH_METADATA | \
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DEV_TX_OFFLOAD_MULTI_SEGS)
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/*
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* Compile time sanity check for vectorized functions.
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*/
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#define S_ASSERT_RTE_MBUF(s) \
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static_assert(s, "A field of struct rte_mbuf is changed")
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#define S_ASSERT_MLX5_CQE(s) \
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static_assert(s, "A field of struct mlx5_cqe is changed")
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/* rxq_cq_decompress_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, hash) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
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/* rxq_cq_to_ptype_oflags_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, ol_flags) ==
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offsetof(struct rte_mbuf, rearm_data) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, rearm_data) ==
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RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
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/* rxq_burst_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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#if (RTE_CACHE_LINE_SIZE == 128)
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 64);
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#else
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 0);
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#endif
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rx_hash_res) ==
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offsetof(struct mlx5_cqe, pkt_info) + 12);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd1) +
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sizeof(((struct mlx5_cqe *)0)->rsvd1) ==
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offsetof(struct mlx5_cqe, hdr_type_etc));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, vlan_info) ==
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offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd2) +
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sizeof(((struct mlx5_cqe *)0)->rsvd2) ==
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offsetof(struct mlx5_cqe, byte_cnt));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, sop_drop_qpn) ==
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RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, op_own) ==
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offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
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/**
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* Replenish buffers for RX in bulk.
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*
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* @param rxq
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* Pointer to RX queue structure.
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* @param n
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* Number of buffers to be replenished.
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*/
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static inline void
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mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
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{
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const uint16_t q_n = 1 << rxq->elts_n;
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const uint16_t q_mask = q_n - 1;
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uint16_t elts_idx = rxq->rq_ci & q_mask;
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struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
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volatile struct mlx5_wqe_data_seg *wq =
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&((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[elts_idx];
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unsigned int i;
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assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n));
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assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
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assert(MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n) > MLX5_VPMD_DESCS_PER_LOOP);
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/* Not to cross queue end. */
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n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
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if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
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rxq->stats.rx_nombuf += n;
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return;
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}
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for (i = 0; i < n; ++i) {
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wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
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RTE_PKTMBUF_HEADROOM);
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/* If there's only one MR, no need to replace LKey in WQE. */
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if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
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wq[i].lkey = mlx5_rx_mb2mr(rxq, elts[i]);
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}
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rxq->rq_ci += n;
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/* Prevent overflowing into consumed mbufs. */
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elts_idx = rxq->rq_ci & q_mask;
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for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
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(*rxq->elts)[elts_idx + i] = &rxq->fake_mbuf;
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rte_cio_wmb();
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*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
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}
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#endif /* RTE_PMD_MLX5_RXTX_VEC_H_ */
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