c388a2f6d7
ConnectX 4-5 support only 40 bytes of RSS key, using a compiled size hash key is not necessary. Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com> Acked-by: Yongseok Koh <yskoh@mellanox.com>
365 lines
8.0 KiB
C
365 lines
8.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2016 6WIND S.A.
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* Copyright 2016 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_PRM_H_
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#define RTE_PMD_MLX5_PRM_H_
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#include <assert.h>
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/mlx5dv.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_vect.h>
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#include "mlx5_autoconf.h"
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/* RSS hash key size. */
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#define MLX5_RSS_HASH_KEY_LEN 40
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/* Get CQE owner bit. */
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#define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
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/* Get CQE format. */
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#define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
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/* Get CQE opcode. */
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#define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
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/* Get CQE solicited event. */
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#define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
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/* Invalidate a CQE. */
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#define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
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/* Maximum number of packets a multi-packet WQE can handle. */
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#define MLX5_MPW_DSEG_MAX 5
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/* WQE DWORD size */
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#define MLX5_WQE_DWORD_SIZE 16
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/* WQE size */
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#define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
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/* Max size of a WQE session. */
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#define MLX5_WQE_SIZE_MAX 960U
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/* Compute the number of DS. */
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#define MLX5_WQE_DS(n) \
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(((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
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/* Room for inline data in multi-packet WQE. */
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#define MLX5_MWQE64_INL_DATA 28
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/* Default minimum number of Tx queues for inlining packets. */
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#define MLX5_EMPW_MIN_TXQS 8
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/* Default max packet length to be inlined. */
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#define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
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#define MLX5_OPC_MOD_ENHANCED_MPSW 0
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#define MLX5_OPCODE_ENHANCED_MPSW 0x29
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/* CQE value to inform that VLAN is stripped. */
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#define MLX5_CQE_VLAN_STRIPPED (1u << 0)
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/* IPv4 options. */
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#define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
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/* IPv6 packet. */
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#define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
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/* IPv4 packet. */
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#define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
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/* TCP packet. */
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#define MLX5_CQE_RX_TCP_PACKET (1u << 4)
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/* UDP packet. */
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#define MLX5_CQE_RX_UDP_PACKET (1u << 5)
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/* IP is fragmented. */
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#define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
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/* L2 header is valid. */
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#define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
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/* L3 header is valid. */
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#define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
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/* L4 header is valid. */
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#define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
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/* Outer packet, 0 IPv4, 1 IPv6. */
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#define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
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/* Tunnel packet bit in the CQE. */
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#define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
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/* Inner L3 checksum offload (Tunneled packets only). */
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#define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
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/* Inner L4 checksum offload (Tunneled packets only). */
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#define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
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/* Outer L4 type is TCP. */
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#define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
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/* Outer L4 type is UDP. */
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#define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
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/* Outer L3 type is IPV4. */
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#define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
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/* Outer L3 type is IPV6. */
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#define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
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/* Inner L4 type is TCP. */
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#define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
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/* Inner L4 type is UDP. */
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#define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
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/* Inner L3 type is IPV4. */
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#define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
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/* Inner L3 type is IPV6. */
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#define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
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/* Is flow mark valid. */
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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#define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
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#else
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#define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
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#endif
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/* INVALID is used by packets matching no flow rules. */
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#define MLX5_FLOW_MARK_INVALID 0
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/* Maximum allowed value to mark a packet. */
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#define MLX5_FLOW_MARK_MAX 0xfffff0
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/* Default mark value used when none is provided. */
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#define MLX5_FLOW_MARK_DEFAULT 0xffffff
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/* Maximum number of DS in WQE. */
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#define MLX5_DSEG_MAX 63
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/* Subset of struct mlx5_wqe_eth_seg. */
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struct mlx5_wqe_eth_seg_small {
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uint32_t rsvd0;
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uint8_t cs_flags;
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uint8_t rsvd1;
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uint16_t mss;
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uint32_t rsvd2;
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uint16_t inline_hdr_sz;
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uint8_t inline_hdr[2];
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} __rte_aligned(MLX5_WQE_DWORD_SIZE);
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struct mlx5_wqe_inl_small {
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uint32_t byte_cnt;
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uint8_t raw;
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} __rte_aligned(MLX5_WQE_DWORD_SIZE);
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struct mlx5_wqe_ctrl {
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uint32_t ctrl0;
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uint32_t ctrl1;
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uint32_t ctrl2;
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uint32_t ctrl3;
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} __rte_aligned(MLX5_WQE_DWORD_SIZE);
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/* Small common part of the WQE. */
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struct mlx5_wqe {
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uint32_t ctrl[4];
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struct mlx5_wqe_eth_seg_small eseg;
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};
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/* Vectorize WQE header. */
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struct mlx5_wqe_v {
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rte_v128u32_t ctrl;
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rte_v128u32_t eseg;
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};
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/* WQE. */
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struct mlx5_wqe64 {
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struct mlx5_wqe hdr;
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uint8_t raw[32];
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} __rte_aligned(MLX5_WQE_SIZE);
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/* MPW mode. */
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enum mlx5_mpw_mode {
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MLX5_MPW_DISABLED,
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MLX5_MPW,
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MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
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};
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/* MPW session status. */
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enum mlx5_mpw_state {
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MLX5_MPW_STATE_OPENED,
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MLX5_MPW_INL_STATE_OPENED,
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MLX5_MPW_ENHANCED_STATE_OPENED,
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MLX5_MPW_STATE_CLOSED,
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};
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/* MPW session descriptor. */
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struct mlx5_mpw {
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enum mlx5_mpw_state state;
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unsigned int pkts_n;
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unsigned int len;
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unsigned int total_len;
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volatile struct mlx5_wqe *wqe;
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union {
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volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
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volatile uint8_t *raw;
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} data;
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};
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/* WQE for Multi-Packet RQ. */
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struct mlx5_wqe_mprq {
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struct mlx5_wqe_srq_next_seg next_seg;
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struct mlx5_wqe_data_seg dseg;
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};
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#define MLX5_MPRQ_LEN_MASK 0x000ffff
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#define MLX5_MPRQ_LEN_SHIFT 0
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#define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
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#define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
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#define MLX5_MPRQ_FILLER_MASK 0x80000000
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#define MLX5_MPRQ_FILLER_SHIFT 31
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#define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
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/* CQ element structure - should be equal to the cache line size */
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struct mlx5_cqe {
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#if (RTE_CACHE_LINE_SIZE == 128)
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uint8_t padding[64];
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#endif
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uint8_t pkt_info;
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uint8_t rsvd0;
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uint16_t wqe_id;
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uint8_t rsvd3[8];
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uint32_t rx_hash_res;
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uint8_t rx_hash_type;
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uint8_t rsvd1[11];
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uint16_t hdr_type_etc;
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uint16_t vlan_info;
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uint8_t rsvd2[12];
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uint32_t byte_cnt;
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uint64_t timestamp;
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uint32_t sop_drop_qpn;
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uint16_t wqe_counter;
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uint8_t rsvd4;
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uint8_t op_own;
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};
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/* Adding direct verbs to data-path. */
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/* CQ sequence number mask. */
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#define MLX5_CQ_SQN_MASK 0x3
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/* CQ sequence number index. */
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#define MLX5_CQ_SQN_OFFSET 28
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/* CQ doorbell index mask. */
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#define MLX5_CI_MASK 0xffffff
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/* CQ doorbell offset. */
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#define MLX5_CQ_ARM_DB 1
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/* CQ doorbell offset*/
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#define MLX5_CQ_DOORBELL 0x20
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/* CQE format value. */
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#define MLX5_COMPRESSED 0x3
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/* CQE format mask. */
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#define MLX5E_CQE_FORMAT_MASK 0xc
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/* MPW opcode. */
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#define MLX5_OPC_MOD_MPW 0x01
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/* Compressed Rx CQE structure. */
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struct mlx5_mini_cqe8 {
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union {
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uint32_t rx_hash_result;
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struct {
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uint16_t checksum;
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uint16_t stride_idx;
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};
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struct {
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uint16_t wqe_counter;
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uint8_t s_wqe_opcode;
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uint8_t reserved;
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} s_wqe_info;
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};
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uint32_t byte_cnt;
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};
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/**
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* Convert a user mark to flow mark.
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*
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* @param val
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* Mark value to convert.
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*
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* @return
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* Converted mark value.
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*/
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static inline uint32_t
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mlx5_flow_mark_set(uint32_t val)
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{
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uint32_t ret;
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/*
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* Add one to the user value to differentiate un-marked flows from
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* marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
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* remains untouched.
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*/
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if (val != MLX5_FLOW_MARK_DEFAULT)
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++val;
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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/*
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* Mark is 24 bits (minus reserved values) but is stored on a 32 bit
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* word, byte-swapped by the kernel on little-endian systems. In this
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* case, left-shifting the resulting big-endian value ensures the
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* least significant 24 bits are retained when converting it back.
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*/
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ret = rte_cpu_to_be_32(val) >> 8;
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#else
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ret = val;
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#endif
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return ret;
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}
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/**
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* Convert a mark to user mark.
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*
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* @param val
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* Mark value to convert.
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*
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* @return
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* Converted mark value.
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*/
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static inline uint32_t
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mlx5_flow_mark_get(uint32_t val)
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{
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/*
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* Subtract one from the retrieved value. It was added by
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* mlx5_flow_mark_set() to distinguish unmarked flows.
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*/
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#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
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return (val >> 8) - 1;
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#else
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return val - 1;
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#endif
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}
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#endif /* RTE_PMD_MLX5_PRM_H_ */
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