2700326085
The mlx5 PMD for regex class uses an MMO WQE operated by the GGA engine in BF devices. Currently, all the MMO WQEs are managed by the SQ object. Starting from BF3, the queue of the MMO WQEs should be connected to the GGA engine using a new configuration, MMO, that will be supported only in the QP object. The FW introduced new capabilities to define whether the MMO configuration should be configured for the GGA queue. Replace all the GGA queue objects to QP, set MMO configuration according to the new FW capabilities. Signed-off-by: Raja Zidane <rzidane@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
140 lines
4.4 KiB
C
140 lines
4.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2020 Mellanox Technologies, Ltd
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*/
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#ifndef MLX5_REGEX_H
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#define MLX5_REGEX_H
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#include <rte_regexdev.h>
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#include <infiniband/verbs.h>
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#include <infiniband/mlx5dv.h>
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#include <mlx5_common.h>
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#include <mlx5_common_mr.h>
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#include <mlx5_common_devx.h>
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#include "mlx5_rxp.h"
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#include "mlx5_regex_utils.h"
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struct mlx5_regex_hw_qp {
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uint16_t log_nb_desc; /* Log 2 number of desc for this object. */
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struct mlx5_devx_qp qp_obj; /* The QP DevX object. */
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size_t pi, db_pi;
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size_t ci;
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uint32_t qpn;
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};
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struct mlx5_regex_cq {
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uint32_t log_nb_desc; /* Log 2 number of desc for this object. */
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struct mlx5_devx_cq cq_obj; /* The CQ DevX object. */
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size_t ci;
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};
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struct mlx5_regex_qp {
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uint32_t flags; /* QP user flags. */
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uint32_t nb_desc; /* Total number of desc for this qp. */
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struct mlx5_regex_hw_qp *qps; /* Pointer to qp array. */
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uint16_t nb_obj; /* Number of qp objects. */
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struct mlx5_regex_cq cq; /* CQ struct. */
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uint32_t free_qps;
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struct mlx5_regex_job *jobs;
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struct ibv_mr *metadata;
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struct ibv_mr *outputs;
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struct ibv_mr *imkey_addr; /* Indirect mkey array region. */
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size_t ci, pi;
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struct mlx5_mr_ctrl mr_ctrl;
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};
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struct mlx5_regex_db {
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void *ptr; /* Pointer to the db memory. */
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uint32_t len; /* The memory len. */
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bool active; /* Active flag. */
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uint8_t db_assigned_to_eng_num;
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/**< To which engine the db is connected. */
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struct mlx5_regex_umem umem;
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/**< The umem struct. */
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};
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struct mlx5_regex_priv {
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TAILQ_ENTRY(mlx5_regex_priv) next;
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struct ibv_context *ctx; /* Device context. */
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struct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */
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uint16_t nb_queues; /* Number of queues. */
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struct mlx5_regex_qp *qps; /* Pointer to the qp array. */
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uint16_t nb_max_matches; /* Max number of matches. */
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enum mlx5_rxp_program_mode prog_mode;
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struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +
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MLX5_RXP_EM_COUNT];
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uint32_t nb_engines; /* Number of RegEx engines. */
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struct mlx5dv_devx_uar *uar; /* UAR object. */
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struct ibv_pd *pd;
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TAILQ_ENTRY(mlx5_regex_priv) mem_event_cb;
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/**< Called by memory event callback. */
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struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
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uint8_t is_bf2; /* The device is BF2 device. */
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uint8_t qp_ts_format; /* Whether SQ supports timestamp formats. */
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uint8_t has_umr; /* The device supports UMR. */
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uint32_t mmo_regex_qp_cap:1;
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uint32_t mmo_regex_sq_cap:1;
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};
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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static inline int
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regex_get_pdn(void *pd, uint32_t *pdn)
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{
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struct mlx5dv_obj obj;
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struct mlx5dv_pd pd_info;
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int ret = 0;
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obj.pd.in = pd;
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obj.pd.out = &pd_info;
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ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
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if (ret) {
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DRV_LOG(DEBUG, "Fail to get PD object info");
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return ret;
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}
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*pdn = pd_info.pdn;
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return 0;
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}
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#endif
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/* mlx5_regex.c */
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int mlx5_regex_start(struct rte_regexdev *dev);
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int mlx5_regex_stop(struct rte_regexdev *dev);
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int mlx5_regex_close(struct rte_regexdev *dev);
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/* mlx5_rxp.c */
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int mlx5_regex_info_get(struct rte_regexdev *dev,
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struct rte_regexdev_info *info);
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int mlx5_regex_configure(struct rte_regexdev *dev,
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const struct rte_regexdev_config *cfg);
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int mlx5_regex_rules_db_import(struct rte_regexdev *dev,
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const char *rule_db, uint32_t rule_db_len);
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/* mlx5_regex_devx.c */
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int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
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uint32_t addr, uint32_t data);
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int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
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uint32_t addr, uint32_t *data);
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int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);
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int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);
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int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
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uint32_t umem_id, uint64_t umem_offset);
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/* mlx5_regex_control.c */
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int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
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const struct rte_regexdev_qp_conf *cfg);
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/* mlx5_regex_fastpath.c */
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int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id);
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void mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv,
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uint32_t qp_id);
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uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,
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struct rte_regex_ops **ops, uint16_t nb_ops);
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uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,
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struct rte_regex_ops **ops, uint16_t nb_ops);
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uint16_t mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id,
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struct rte_regex_ops **ops, uint16_t nb_ops);
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#endif /* MLX5_REGEX_H */
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