395 lines
13 KiB
C
395 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
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* Copyright(c) 2018 Synopsys, Inc. All rights reserved.
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*/
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#include "axgbe_ethdev.h"
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#include "axgbe_common.h"
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#include "axgbe_phy.h"
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static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
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static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
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/* The set of PCI devices this driver supports */
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#define AMD_PCI_VENDOR_ID 0x1022
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#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
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#define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
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int axgbe_logtype_init;
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int axgbe_logtype_driver;
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static const struct rte_pci_id pci_id_axgbe_map[] = {
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{RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
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{RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
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{ .vendor_id = 0, },
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};
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static struct axgbe_version_data axgbe_v2a = {
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.xpcs_access = AXGBE_XPCS_ACCESS_V2,
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.mmc_64bit = 1,
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.tx_max_fifo_size = 229376,
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.rx_max_fifo_size = 229376,
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.tx_tstamp_workaround = 1,
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.ecc_support = 1,
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.i2c_support = 1,
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};
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static struct axgbe_version_data axgbe_v2b = {
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.xpcs_access = AXGBE_XPCS_ACCESS_V2,
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.mmc_64bit = 1,
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.tx_max_fifo_size = 65536,
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.rx_max_fifo_size = 65536,
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.tx_tstamp_workaround = 1,
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.ecc_support = 1,
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.i2c_support = 1,
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};
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static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
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{
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unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
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struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
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mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
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mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
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mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
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memset(hw_feat, 0, sizeof(*hw_feat));
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hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
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/* Hardware feature register 0 */
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hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
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hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
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hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
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hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
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hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
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hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
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hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
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hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
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hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
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hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
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hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
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hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
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ADDMACADRSEL);
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hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
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hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
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/* Hardware feature register 1 */
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hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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RXFIFOSIZE);
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hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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TXFIFOSIZE);
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hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
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MAC_HWF1R, ADVTHWORD);
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hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
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hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
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hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
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hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
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hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
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hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
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hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
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hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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HASHTBLSZ);
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hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
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L3L4FNUM);
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/* Hardware feature register 2 */
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hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
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hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
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hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
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hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
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hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
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hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
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AUXSNAPNUM);
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/* Translate the Hash Table size into actual number */
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switch (hw_feat->hash_table_size) {
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case 0:
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break;
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case 1:
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hw_feat->hash_table_size = 64;
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break;
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case 2:
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hw_feat->hash_table_size = 128;
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break;
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case 3:
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hw_feat->hash_table_size = 256;
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break;
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}
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/* Translate the address width setting into actual number */
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switch (hw_feat->dma_width) {
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case 0:
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hw_feat->dma_width = 32;
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break;
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case 1:
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hw_feat->dma_width = 40;
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break;
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case 2:
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hw_feat->dma_width = 48;
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break;
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default:
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hw_feat->dma_width = 32;
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}
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/* The Queue, Channel and TC counts are zero based so increment them
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* to get the actual number
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*/
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hw_feat->rx_q_cnt++;
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hw_feat->tx_q_cnt++;
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hw_feat->rx_ch_cnt++;
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hw_feat->tx_ch_cnt++;
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hw_feat->tc_cnt++;
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/* Translate the fifo sizes into actual numbers */
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hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
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hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
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}
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static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
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{
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axgbe_init_function_ptrs_dev(&pdata->hw_if);
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}
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static void axgbe_set_counts(struct axgbe_port *pdata)
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{
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/* Set all the function pointers */
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axgbe_init_all_fptrs(pdata);
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/* Populate the hardware features */
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axgbe_get_all_hw_features(pdata);
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/* Set default max values if not provided */
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if (!pdata->tx_max_channel_count)
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pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
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if (!pdata->rx_max_channel_count)
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pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
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if (!pdata->tx_max_q_count)
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pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
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if (!pdata->rx_max_q_count)
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pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
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/* Calculate the number of Tx and Rx rings to be created
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* -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
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* the number of Tx queues to the number of Tx channels
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* enabled
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* -Rx (DMA) Channels do not map 1-to-1 so use the actual
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* number of Rx queues or maximum allowed
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*/
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pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
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pdata->tx_max_channel_count);
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pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
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pdata->tx_max_q_count);
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pdata->tx_q_count = pdata->tx_ring_count;
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pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
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pdata->rx_max_channel_count);
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pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
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pdata->rx_max_q_count);
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}
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static void axgbe_default_config(struct axgbe_port *pdata)
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{
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pdata->pblx8 = DMA_PBL_X8_ENABLE;
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pdata->tx_sf_mode = MTL_TSF_ENABLE;
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pdata->tx_threshold = MTL_TX_THRESHOLD_64;
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pdata->tx_pbl = DMA_PBL_32;
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pdata->tx_osp_mode = DMA_OSP_ENABLE;
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pdata->rx_sf_mode = MTL_RSF_ENABLE;
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pdata->rx_threshold = MTL_RX_THRESHOLD_64;
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pdata->rx_pbl = DMA_PBL_32;
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pdata->pause_autoneg = 1;
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pdata->tx_pause = 0;
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pdata->rx_pause = 0;
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pdata->phy_speed = SPEED_UNKNOWN;
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pdata->power_down = 0;
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}
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/*
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* It returns 0 on success.
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*/
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static int
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eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
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{
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PMD_INIT_FUNC_TRACE();
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struct axgbe_port *pdata;
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struct rte_pci_device *pci_dev;
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uint32_t reg, mac_lo, mac_hi;
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int ret;
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/*
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* For secondary processes, we don't initialise any further as primary
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* has already done this work.
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*/
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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pdata = (struct axgbe_port *)eth_dev->data->dev_private;
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/* initial state */
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axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
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axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
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pdata->eth_dev = eth_dev;
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pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
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pdata->pci_dev = pci_dev;
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pdata->xgmac_regs =
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(uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
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pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;
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pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;
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pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
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/* version specific driver data*/
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if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
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pdata->vdata = &axgbe_v2a;
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else
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pdata->vdata = &axgbe_v2b;
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/* Configure the PCS indirect addressing support */
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reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF);
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pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
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pdata->xpcs_window <<= 6;
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pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
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pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
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pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
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pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
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PMD_INIT_LOG(DEBUG,
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"xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
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pdata->xpcs_window_size, pdata->xpcs_window_mask);
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XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
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/* Retrieve the MAC address */
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mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
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mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
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pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
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pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
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pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
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pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
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pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
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pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
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eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
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ETHER_ADDR_LEN, 0);
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if (!eth_dev->data->mac_addrs) {
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PMD_INIT_LOG(ERR,
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"Failed to alloc %u bytes needed to store MAC addr tbl",
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ETHER_ADDR_LEN);
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return -ENOMEM;
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}
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if (!is_valid_assigned_ether_addr(&pdata->mac_addr))
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eth_random_addr(pdata->mac_addr.addr_bytes);
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/* Copy the permanent MAC address */
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ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
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/* Clock settings */
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pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
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pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
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/* Set the DMA coherency values */
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pdata->coherent = 1;
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pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
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pdata->arcache = AXGBE_DMA_OS_ARCACHE;
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pdata->awcache = AXGBE_DMA_OS_AWCACHE;
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/* Set the maximum channels and queues */
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reg = XP_IOREAD(pdata, XP_PROP_1);
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pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
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pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
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pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
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pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
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/* Set the hardware channel and queue counts */
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axgbe_set_counts(pdata);
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/* Set the maximum fifo amounts */
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reg = XP_IOREAD(pdata, XP_PROP_2);
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pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
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pdata->tx_max_fifo_size *= 16384;
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pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
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pdata->vdata->tx_max_fifo_size);
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pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
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pdata->rx_max_fifo_size *= 16384;
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pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
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pdata->vdata->rx_max_fifo_size);
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/* Issue software reset to DMA */
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ret = pdata->hw_if.exit(pdata);
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if (ret)
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PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
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/* Set default configuration data */
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axgbe_default_config(pdata);
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/* Set default max values if not provided */
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if (!pdata->tx_max_fifo_size)
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pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
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if (!pdata->rx_max_fifo_size)
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pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
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pthread_mutex_init(&pdata->xpcs_mutex, NULL);
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pthread_mutex_init(&pdata->i2c_mutex, NULL);
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pthread_mutex_init(&pdata->an_mutex, NULL);
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pthread_mutex_init(&pdata->phy_mutex, NULL);
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PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
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eth_dev->data->port_id, pci_dev->id.vendor_id,
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pci_dev->id.device_id);
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return 0;
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}
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static int
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eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
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{
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PMD_INIT_FUNC_TRACE();
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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/*Free macaddres*/
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rte_free(eth_dev->data->mac_addrs);
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eth_dev->data->mac_addrs = NULL;
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return 0;
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}
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static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
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struct rte_pci_device *pci_dev)
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{
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return rte_eth_dev_pci_generic_probe(pci_dev,
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sizeof(struct axgbe_port), eth_axgbe_dev_init);
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}
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static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
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{
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return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
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}
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static struct rte_pci_driver rte_axgbe_pmd = {
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.id_table = pci_id_axgbe_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
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.probe = eth_axgbe_pci_probe,
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.remove = eth_axgbe_pci_remove,
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};
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RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
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RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
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RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
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RTE_INIT(axgbe_init_log);
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static void
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axgbe_init_log(void)
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{
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axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
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if (axgbe_logtype_init >= 0)
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rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
|
|
axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
|
|
if (axgbe_logtype_driver >= 0)
|
|
rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);
|
|
}
|