a61b319674
Added changes to enable CMAN (RED or PIE) at init from profile configuration file. By default CMAN code is enabled but not in use, when there is no RED or PIE profile configured. Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com> Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
184 lines
4.2 KiB
C
184 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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*/
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#ifndef _MAIN_H_
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#define _MAIN_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rte_sched.h>
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#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1
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/*
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* Configurable number of RX/TX ring descriptors
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*/
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#define APP_INTERACTIVE_DEFAULT 0
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#define APP_RX_DESC_DEFAULT 1024
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#define APP_TX_DESC_DEFAULT 1024
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#define APP_RING_SIZE (8*1024)
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#define NB_MBUF (2*1024*1024)
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#define MAX_PKT_RX_BURST 64
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#define PKT_ENQUEUE 64
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#define PKT_DEQUEUE 32
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#define MAX_PKT_TX_BURST 64
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#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
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#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
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#define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
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#define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
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#define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */
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#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */
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#define BURST_TX_DRAIN_US 100
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#ifndef APP_MAX_LCORE
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#if (RTE_MAX_LCORE > 64)
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#define APP_MAX_LCORE 64
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#else
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#define APP_MAX_LCORE RTE_MAX_LCORE
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#endif
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#endif
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#define MAX_DATA_STREAMS (APP_MAX_LCORE/2)
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#define MAX_SCHED_SUBPORTS 8
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#define MAX_SCHED_PIPES 4096
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#define MAX_SCHED_PIPE_PROFILES 256
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#define MAX_SCHED_SUBPORT_PROFILES 8
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#ifndef APP_COLLECT_STAT
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#define APP_COLLECT_STAT 1
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#endif
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#if APP_COLLECT_STAT
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#define APP_STATS_ADD(stat,val) (stat) += (val)
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#else
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#define APP_STATS_ADD(stat,val) do {(void) (val);} while (0)
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#endif
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#define APP_QAVG_NTIMES 10
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#define APP_QAVG_PERIOD 100
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struct thread_stat
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{
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uint64_t nb_rx;
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uint64_t nb_drop;
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};
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struct thread_conf
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{
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uint32_t counter;
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uint32_t n_mbufs;
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struct rte_mbuf **m_table;
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uint16_t rx_port;
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uint16_t tx_port;
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uint16_t rx_queue;
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uint16_t tx_queue;
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struct rte_ring *rx_ring;
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struct rte_ring *tx_ring;
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struct rte_sched_port *sched_port;
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#if APP_COLLECT_STAT
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struct thread_stat stat;
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#endif
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} __rte_cache_aligned;
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struct flow_conf
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{
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uint32_t rx_core;
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uint32_t wt_core;
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uint32_t tx_core;
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uint16_t rx_port;
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uint16_t tx_port;
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uint16_t rx_queue;
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uint16_t tx_queue;
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struct rte_ring *rx_ring;
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struct rte_ring *tx_ring;
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struct rte_sched_port *sched_port;
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struct rte_mempool *mbuf_pool;
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struct thread_conf rx_thread;
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struct thread_conf wt_thread;
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struct thread_conf tx_thread;
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};
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struct ring_conf
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{
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uint32_t rx_size;
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uint32_t ring_size;
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uint32_t tx_size;
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};
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struct burst_conf
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{
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uint16_t rx_burst;
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uint16_t ring_burst;
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uint16_t qos_dequeue;
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uint16_t tx_burst;
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};
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struct ring_thresh
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{
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uint8_t pthresh; /**< Ring prefetch threshold. */
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uint8_t hthresh; /**< Ring host threshold. */
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uint8_t wthresh; /**< Ring writeback threshold. */
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};
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extern uint8_t interactive;
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extern uint32_t qavg_period;
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extern uint32_t qavg_ntimes;
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extern uint32_t nb_pfc;
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extern const char *cfg_profile;
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extern int mp_size;
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extern struct flow_conf qos_conf[];
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extern int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];
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extern struct ring_conf ring_conf;
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extern struct burst_conf burst_conf;
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extern struct ring_thresh rx_thresh;
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extern struct ring_thresh tx_thresh;
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extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
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extern uint32_t n_active_queues;
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extern struct rte_sched_port_params port_params;
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extern struct rte_sched_cman_params cman_params;
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extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
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int app_parse_args(int argc, char **argv);
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int app_init(void);
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void prompt(void);
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void app_rx_thread(struct thread_conf **qconf);
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void app_tx_thread(struct thread_conf **qconf);
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void app_worker_thread(struct thread_conf **qconf);
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void app_mixed_thread(struct thread_conf **qconf);
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void app_stat(void);
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int subport_stat(uint16_t port_id, uint32_t subport_id);
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int pipe_stat(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id);
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int qavg_q(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id,
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uint8_t tc, uint8_t q);
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int qavg_tcpipe(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id,
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uint8_t tc);
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int qavg_pipe(uint16_t port_id, uint32_t subport_id, uint32_t pipe_id);
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int qavg_tcsubport(uint16_t port_id, uint32_t subport_id, uint8_t tc);
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int qavg_subport(uint16_t port_id, uint32_t subport_id);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _MAIN_H_ */
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