ec94dbc573
The base driver is the backend module for the QLogic FastLinQ QL4xxxx 25G/40G CNA family of adapters as well as their virtual functions (VF) in SR-IOV context. The purpose of the base module is to: - provide all the common code that will be shared between the various drivers that would be used with said line of products. Flows such as chip initialization and de-initialization fall under this category. - abstract the protocol-specific HW & FW components, allowing the protocol drivers to have clean APIs, which are detached in its slowpath configuration from the actual Hardware Software Interface(HSI). This patch adds a base module without any protocol-specific bits. I.e., this adds a basic implementation that almost entirely falls under the first category. Signed-off-by: Harish Patil <harish.patil@qlogic.com> Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com> Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
32 lines
950 B
C
32 lines
950 B
C
/*
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* Copyright (c) 2016 QLogic Corporation.
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* All rights reserved.
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* www.qlogic.com
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*
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* See LICENSE.qede_pmd for copyright and licensing details.
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*/
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#ifndef __ECORE_UTILS_H__
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#define __ECORE_UTILS_H__
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/* dma_addr_t manip */
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#define DMA_LO(x) ((u32)(((dma_addr_t)(x)) & 0xffffffff))
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#define DMA_HI(x) ((u32)(((dma_addr_t)(x)) >> 32))
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#define DMA_LO_LE(x) OSAL_CPU_TO_LE32(DMA_LO(x))
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#define DMA_HI_LE(x) OSAL_CPU_TO_LE32(DMA_HI(x))
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/* It's assumed that whoever includes this has previously included an hsi
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* file defining the regpair.
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*/
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#define DMA_REGPAIR_LE(x, val) (x).hi = DMA_HI_LE((val)); \
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(x).lo = DMA_LO_LE((val))
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#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
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#define HILO_DMA(hi, lo) HILO_GEN(hi, lo, dma_addr_t)
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#define HILO_64(hi, lo) HILO_GEN(hi, lo, u64)
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#define HILO_DMA_REGPAIR(regpair) (HILO_DMA(regpair.hi, regpair.lo))
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#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
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#endif
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