f513f62059
Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2016-2019 NXP
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*
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*/
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#ifndef _DPAA2_HW_DPBP_H_
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#define _DPAA2_HW_DPBP_H_
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#define DPAA2_MAX_BUF_POOLS 8
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#define DPAA2_INVALID_MBUF_SEQN 0
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struct buf_pool_cfg {
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void *addr;
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/**< The address from where DPAA2 will carve out the buffers */
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rte_iova_t phys_addr;
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/**< Physical address of the memory provided in addr */
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uint32_t num;
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/**< Number of buffers */
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uint32_t size;
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/**< Size including headroom for each buffer */
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uint16_t align;
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/**< Buffer alignment (in bytes) */
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uint16_t bpid;
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/**< Autogenerated buffer pool ID for internal use */
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};
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struct buf_pool {
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uint32_t size; /**< Size of the Pool */
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uint32_t num_bufs; /**< Number of buffers in Pool */
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uint16_t bpid; /**< Pool ID, from pool configuration */
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uint8_t *h_bpool_mem; /**< Internal context data */
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struct dpaa2_dpbp_dev *dpbp_node; /**< Hardware context */
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};
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/*!
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* Buffer pool list configuration structure. User need to give DPAA2 the
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* valid number of 'num_buf_pools'.
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*/
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struct dpaa2_bp_list_cfg {
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struct buf_pool_cfg buf_pool; /* Configuration of each buffer pool*/
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};
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struct dpaa2_bp_list {
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struct dpaa2_bp_list *next;
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struct rte_mempool *mp; /**< DPDK RTE EAL pool reference */
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int32_t dpaa2_ops_index; /**< Index into DPDK Mempool ops table */
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struct buf_pool buf_pool;
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};
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struct dpaa2_bp_info {
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uint32_t meta_data_size;
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uint32_t bpid;
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struct dpaa2_bp_list *bp_list;
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};
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#define mempool_to_bpinfo(mp) ((struct dpaa2_bp_info *)(mp)->pool_data)
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#define mempool_to_bpid(mp) ((mempool_to_bpinfo(mp))->bpid)
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extern struct dpaa2_bp_info *rte_dpaa2_bpid_info;
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int rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool,
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void **obj_table, unsigned int count);
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#endif /* _DPAA2_HW_DPBP_H_ */
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